Monte Cimone v2: Down the Road of RISC-V High-Performance Computers

2025-03-24

AI Summary

This work addresses the challenge of deploying RISC-V in high-performance computing (HPC) by conducting the first systematic end-to-end evaluation of a commercial RISC-V SoC—Sophgo SG2042 featuring the Vector Extension (RVV)—on real HPC workloads (HPL and Stream). We perform deep optimization across the Linux HPC software stack, compilers (GCC/Rust), and open-source math libraries to identify critical bottlenecks in automatic vectorization and library-level optimization within the current RVV ecosystem. Results demonstrate 127× improvement in double-precision floating-point performance (HPL) and 69× increase in memory bandwidth (Stream) over baseline configurations. The study validates the initial feasibility of RISC-V for datacenter-scale HPC deployments and establishes a reproducible methodology and empirical benchmark suite for hardware–software co-optimization of RVV-based systems.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Learning & Optimization for CV
• Search and Optimization: Evaluation and Analysis

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• Security and Privacy: Large-scale security measurements

Abstract

Many RISC-V platforms and SoCs have been announced in recent years targeting the HPC sector, but only a few of them are commercially available and engineered to fit the HPC requirements. The Monte Cimone project targeted assessing their capabilities and maturity, aiming to make RISC-V a competitive choice when building a datacenter. Nowadays, RV SoCs with vector extension, form factor and memory capacity suitable for HPC applications are available in the market, but it is unclear how compilers and open-source libraries can take advantage of its performance. In this paper, we describe the performance assessment of the upgrade of the Monte Cimone (MCv2) cluster with the Sophgo SG2042 processor's HPC operations. The upgrade increases the attained node's performance by 127x on HPL DP FLOP/s and 69x on Stream Memory Bandwidth.

Problem

• Assessing RISC-V capabilities for HPC competitiveness
• Evaluating compiler and library performance on RISC-V
• Upgrading Monte Cimone cluster with Sophgo SG2042 processor

Innovation

• RISC-V HPC cluster performance assessment
• Sophgo SG2042 processor upgrade
• 127x HPL DP FLOP/s improvement