Counterexample Classification against Signal Temporal Logic Specifications

2026-01-20

AI Summary

This work addresses the challenge of diverse and poorly attributed counterexamples in Signal Temporal Logic (STL) verification. To enable efficient fault localization, the authors propose a novel counterexample classification method based on Parametric Signal Temporal Logic (PSTL). Specifically, they design PSTL templates tailored to distinct classes of system faults and exploit inclusion relationships among these classes to construct a binary search–based identification algorithm, substantially reducing the number of queries required for classification. This study presents the first formal application of PSTL to counterexample categorization, achieving effective root-cause attribution. Experimental evaluation on two benchmark systems demonstrates that the prototype tool accurately classifies counterexamples, significantly enhancing debugging efficiency.

Technology Category

• Knowledge Representation and Reasoning: Diagnosis and Abductive Reasoning
• Reasoning under Uncertainty: Stochastic Optimization
• Constraint Satisfaction and Optimization: Satisfiability Modulo Theories

Application Category

• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• User Modeling, Personalization and Recommendation: Attacks and countermeasures in recommendation systems
• Security and Privacy: Tracking, profiling, and countermeasures against them

Abstract

Signal Temporal Logic (STL) has been widely adopted as a specification language for specifying desirable behaviors of hybrid systems. By monitoring a given STL specification, we can detect the executions that violate it, which are often referred to as counterexamples. In practice, these counterexamples may arise from different causes and thus are relevant to different system defects. To effectively address this, we need a proper criterion for classifying these counterexamples, by which we can comprehend the possible violation patterns and the distributions of these counterexamples with respect to the patterns. In this paper, we propose a classification criterion by using parametric signal temporal logic (PSTL) to represent each class. Due to this formalism, identifying the classes of a counterexample requires finding proper parameter values of PSTL that enable a class to include the counterexample. To improve the efficiency of class identification, we further derive an inclusion relation between different classes, and then propose a binary search-like approach over it that significantly prunes the classes needed to query. We implement a prototype tool and experimentally evaluate its effectiveness on two widely-studied systems.

Problem

• Counterexample Classification
• Signal Temporal Logic
• Hybrid Systems
• Violation Patterns
• System Defects

Innovation

• Counterexample Classification
• Parametric Signal Temporal Logic
• STL Violation Patterns
• Binary Search over Class Inclusion
• Hybrid System Verification