🤖 AI Summary
This work addresses the reliability challenges in 3D chip stacking arising from process scaling—such as the transition from FinFET to GAAFET—and heterogeneous chiplet integration. In collaboration with leading European research institutions, the project presents the first open-source reliability analysis toolchain tailored for 2.5D/3D VLSI systems. The toolchain integrates multi-scale modeling across physical and system levels, leveraging advanced algorithms within an open-source EDA framework to enable comprehensive reliability assessment in heterogeneous chiplet integration scenarios. Its modular and extensible architecture significantly enhances the capability to predict and optimize reliability during the design phase of 3D integrated systems.
📝 Abstract
As semiconductor manufacturing advances from the 3-nm process toward the sub-nanometer regime and transitions from FinFETs to gate-all-around field-effect transistors (GAAFETs), the resulting complexity and manufacturing challenges continue to increase. In this context, 3D chiplet-based approaches have emerged as key enablers to address these limitations while exploiting the expanded design space. Specifically, chiplets help address the lower yields typically associated with large monolithic designs. This paradigm enables the modular design of heterogeneous systems consisting of multiple chiplets (e.g., CPUs, GPUs, memory) fabricated using different technology nodes and processes. Consequently, it offers a capable and cost-effective strategy for designing heterogeneous systems. This paper introduces the Horizon Europe Twinning project COIN-3D (Collaborative Innovation in 3D VLSI Reliability), which aims to strengthen research excellence in 2.5D/3D VLSI systems reliability through collaboration between leading European institutions. More specifically, our primary scientific goal is the provision of novel open-source Electronic Design Automation (EDA) tools for reliability assessment of 3D systems, integrating advanced algorithms for physical- and system-level reliability analysis.