GROOT: Graph Edge Re-growth and Partitioning for the Verification of Large Designs in Logic Synthesis

2025-11-23

AI Summary

To address the low efficiency and high resource consumption of traditional methods in large-scale circuit verification, this paper proposes GROOT—a framework that pioneers synergistic optimization of chip design knowledge, graph neural networks (GNNs), and GPU kernels. Its key contributions are: (1) domain-aware feature modeling based on And-Inverter Graphs (AIGs), integrating node types and polarity-aware edge connectivity; (2) a graph partitioning and edge-resynthesis algorithm that accelerates computation while preserving verification accuracy; and (3) EDA-specific GPU kernels—HD-kernel for high-density subgraphs and LD-kernel for low-density ones. Evaluated on a 1024-bit carry-save adder (CSA) multiplier verification task, GROOT achieves 99.96% accuracy, reduces memory footprint by 59.38%, and outperforms cuSPARSE, MergePath-SpMM, and GNNAdvisor by 1.10×, 5.80×, and 1.47× in speed, respectively.

Technology Category

• Machine Learning: Hardware-aware ML
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Data Mining & Knowledge Management: Graph Mining, Social Network Analysis & Community

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems

Abstract

Traditional verification methods in chip design are highly time-consuming and computationally demanding, especially for large scale circuits. Graph neural networks (GNNs) have gained popularity as a potential solution to improve verification efficiency. However, there lacks a joint framework that considers all chip design domain knowledge, graph theory, and GPU kernel designs. To address this challenge, we introduce GROOT, an algorithm and system co-design framework that contains chip design domain knowledge and redesigned GPU kernels, to improve verification efficiency. More specifically, we create node features utilizing the circuit node types and the polarity of the connections between the input edges to nodes in And-Inverter Graphs (AIGs). We utilize a graph partitioning algorithm to divide the large graphs into smaller sub-graphs for fast GPU processing and develop a graph edge re-growth algorithm to recover verification accuracy. We carefully profile the EDA graph workloads and observe the uniqueness of their polarized distribution of high degree (HD) nodes and low degree (LD) nodes. We redesign two GPU kernels (HD-kernel and LD-kernel), to fit the EDA graph learning workload on a single GPU. We compare the results with state-of-the-art (SOTA) methods: GAMORA, a GNN-based approach, and the traditional ABC framework. Results show that GROOT achieves a significant reduction in memory footprint (59.38 %), with high accuracy (99.96%) for a very large CSA multiplier, i.e. 1,024 bits with a batch size of 16, which consists of 134,103,040 nodes and 268,140,544 edges. We compare GROOT with GPU-based GPU Kernel designs SOTAs such as cuSPARSE, MergePath-SpMM, and GNNAdvisor. We achieve up to 1.104x, 5.796x, and 1.469x improvement in runtime, respectively.

Problem

• Improves chip design verification efficiency using GNNs
• Addresses lack of integrated framework for circuit verification
• Reduces memory footprint while maintaining high accuracy

Innovation

• Joint framework integrating chip design knowledge and GPU kernels
• Graph partitioning and edge re-growth for efficient verification
• Redesigned GPU kernels for polarized node degree distribution