Register Dispersion: Reducing the Footprint of the Vector Register File in Vector Engines of Low-Cost RISC-V CPUs

2025-03-21

AI Summary

To address the excessive area and power consumption of vector register files (VRFs) in cost-sensitive RISC-V edge processors—hindering efficient vector unit integration—this paper proposes Register Dispersion, a novel hardware mechanism. It restructures the VRF as a small, physically compact register structure supporting dynamic mapping and cache-like management, while maintaining full compliance with the RISC-V Vector ISA. Leveraging spatial and temporal locality in vector register accesses, the mechanism employs an LRU-based cache mapping and replacement policy, hardware-assisted virtual-to-physical address translation, and overflow spill-and-fill handling to enable on-demand register residency. Experimental evaluation shows a 47% reduction in VRF area and a 39% decrease in power consumption, with less than 2% performance degradation on representative machine learning kernels. This significantly enhances the feasibility of integrating high-efficiency vector units into ultra-low-power RISC-V chips.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Learning & Optimization for CV
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Virtualization and resource management in Web systems and infrastructures
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines

Abstract

The deployment of Machine Learning (ML) applications at the edge on resource-constrained devices has accentuated the need for efficient ML processing on low-cost processors. While traditional CPUs provide programming flexibility, their general-purpose architecture often lacks the throughput required for complex ML models. The augmentation of a RISC-V processor with a vector unit can provide substantial data-level parallelism. However, increasing the data-level parallelism supported by vector processing would make the Vector Register File (VRF) a major area consumer in ultra low-cost processors, since 32 vector registers are required for RISC-V Vector ISA compliance. This work leverages the insight that many ML vectorized kernels require a small number of active vector registers, and proposes the use of a physically smaller VRF that dynamically caches only the vector registers currently accessed by the application. This approach, called Register Dispersion, maps the architectural vector registers to a smaller set of physical registers. The proposed ISA-compliant VRF is significantly smaller than a full-size VRF and operates like a conventional cache, i.e., it only stores the most recently accessed vector registers. Essential registers remain readily accessible within the compact VRF, while the others are offloaded to the cache/memory sub-system. The compact VRF design is demonstrated to yield substantial area and power savings, as compared to using a full VRF, with no or minimal impact on performance. This effective trade-off renders the inclusion of vector units in low-cost processors feasible and practical.

Problem

• Reducing VRF footprint in low-cost RISC-V CPUs for ML
• Dynamic caching of active vector registers for efficiency
• Enabling vector units in resource-constrained edge devices

Innovation

• Dynamic caching of active vector registers
• Smaller VRF mapping architectural registers
• Area and power savings with minimal performance impact