TB or Not TB: Coverage-Driven Direct Preference Optimization for Verilog Stimulus Generation

2025-11-19

AI Summary

To address the inefficiency and labor-intensive nature of manually crafting test stimuli in hardware verification, this paper proposes a coverage-driven stimulus generation framework leveraging large language models (LLMs). The method introduces a novel preference learning objective that explicitly incorporates quantitative simulation coverage feedback—marking the first such integration for hardware verification. We construct PairaNet, a domain-specific paired dataset tailored to Verilog testbench generation, and design Coverage-Driven Direct Preference Optimization (CD-DPO), a fine-tuning algorithm that steers LLMs toward synthesizing high-coverage stimuli. Evaluated on the CVDP CID12 benchmark, our approach achieves up to 77.27% higher code coverage than the best open-source and commercial baselines. It significantly accelerates verification convergence while reducing both human effort and computational overhead.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Sampling/Simulation-based Search
• Natural Language Processing: Code Generation / Program Synthesis from Natural Language

Application Category

• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Search and Retrieval-Augmented AI: Web evaluation methodologies and metrics
• User Modeling, Personalization and Recommendation: Large Language Models (LLM) for user modeling and recommendation

Abstract

With the rapid advancement of Large Language Models (LLMs), there is growing interest in applying them to hardware design and verification. Among these stages, design verification remains the most time-consuming and resource-intensive phase, where generating effective stimuli for the design under test (DUT) is both critical and labor-intensive. We present {it TB or not TB}, a framework for automated stimulus generation using LLMs fine-tuned through Coverage-Driven Direct Preference Optimization (CD-DPO). To enable preference-based training, we introduce PairaNet, a dataset derived from PyraNet that pairs high- and low-quality testbenches labeled using simulation-derived coverage metrics. The proposed CD-DPO method integrates quantitative coverage feedback directly into the optimization objective, guiding the model toward generating stimuli that maximize verification coverage. Experiments on the CVDP CID12 benchmark show that {it TB or not TB} outperforms both open-source and commercial baselines, achieving up to 77.27% improvement in code coverage, demonstrating the effectiveness of Coverage-driven preference optimization for LLM-based hardware verification.

Problem

• Automating hardware verification stimulus generation using fine-tuned LLMs
• Maximizing verification coverage through coverage-driven preference optimization
• Reducing labor-intensive testbench creation for design verification

Innovation

• Uses Coverage-Driven Direct Preference Optimization for fine-tuning
• Introduces PairaNet dataset with coverage-labeled testbench pairs
• Integrates quantitative coverage feedback into LLM optimization objective