CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-based CIM Architectures

2025-11-20

AI Summary

SRAM-based compute-in-memory (CIM) architectures face three key challenges in accelerating sparse deep neural networks (DNNs): rigid array constraints, heterogeneous sparsity patterns, and the lack of a unified modeling framework for multi-macro CIM systems. To address these, this paper proposes CIMinus—the first unified framework enabling fine-grained sparsity modeling and analysis for multi-macro CIM systems. Its core innovation lies in a system-level co-modeling methodology for sparse DNNs and CIM hardware, integrating component-level energy breakdown with end-to-end latency estimation, and supporting joint quantification of energy efficiency and latency across diverse dataflows and mapping strategies. Experimental evaluation demonstrates that CIMinus accurately uncovers the impact mechanisms of sparsity patterns and mapping strategies on real-world performance, achieving high-accuracy prediction of both acceleration gains and bottlenecks in two representative scenarios—thereby bridging the gap between theoretical design and hardware deployment.

Technology Category

• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Machine Learning: Hardware-aware ML
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Graph Algorithms and Modeling for the Web: Algorithms and analysis for incomplete, noisy, or partially observed Web-related graphs
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Web Mining and Content Analysis: Large pretrained models with web data

Abstract

Compute-in-memory (CIM) has emerged as a pivotal direction for accelerating workloads in the field of machine learning, such as Deep Neural Networks (DNNs). However, the effective exploitation of sparsity in CIM systems presents numerous challenges, due to the inherent limitations in their rigid array structures. Designing sparse DNN dataflows and developing efficient mapping strategies also become more complex when accounting for diverse sparsity patterns and the flexibility of a multi-macro CIM structure. Despite these complexities, there is still an absence of a unified systematic view and modeling approach for diverse sparse DNN workloads in CIM systems. In this paper, we propose CIMinus, a framework dedicated to cost modeling for sparse DNN workloads on CIM architectures. It provides an in-depth energy consumption analysis at the level of individual components and an assessment of the overall workload latency. We validate CIMinus against contemporary CIM architectures and demonstrate its applicability in two use-cases. These cases provide valuable insights into both the impact of sparsity patterns and the effectiveness of mapping strategies, bridging the gap between theoretical design and practical implementation.

Problem

• Modeling sparse DNN workloads on SRAM-based CIM architectures
• Addressing challenges of exploiting sparsity in rigid CIM array structures
• Providing energy and latency analysis for sparse DNN dataflows

Innovation

• Framework for sparse DNN workload cost modeling
• Analyzes energy consumption at component level
• Assesses overall workload latency on CIM architectures