CorrectHDL: Agentic HDL Design with LLMs Leveraging High-Level Synthesis as Reference

2025-11-20

AI Summary

Large language models (LLMs) often introduce functional errors in hardware description language (HDL) generation due to hallucination. This paper proposes CorrectHDL, the first LLM-based intelligent agent framework that leverages high-level synthesis (HLS) output as a *dynamic functional reference*—not a static target—to guide HDL generation. It integrates retrieval-augmented generation (RAG)-enhanced prompting, functional simulation-based verification, and iterative correction to jointly optimize functional correctness and hardware efficiency. Evaluated on benchmark circuits, CorrectHDL achieves 100% functional correctness while generating implementations with significantly smaller area and lower power consumption than conventional HLS tools—and approaching hand-designed RTL quality. The core innovation lies in transforming HLS results from a fixed specification into an adaptive, simulation-validated correction baseline, thereby enabling tight integration of generative design with formal verification. This validates the efficacy of a closed-loop “generate–verify–correct” paradigm for trustworthy HDL synthesis.

Technology Category

• Machine Learning: Hardware-aware ML
• Natural Language Processing: Code Generation / Program Synthesis from Natural Language
• Cognitive Modeling & Cognitive Systems: Agent Architectures

Application Category

• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems
• Search and Retrieval-Augmented AI: Large language models for search
• Semantics and Knowledge: Data modeling to support human-machine intelligence, including LLMs agents, intelligent system behavior, explanations, and user-friendly interactions

Abstract

Large Language Models (LLMs) have demonstrated remarkable potential in hardware front-end design using hardware description languages (HDLs). However, their inherent tendency toward hallucination often introduces functional errors into the generated HDL designs. To address this issue, we propose the framework CorrectHDL that leverages high-level synthesis (HLS) results as functional references to correct potential errors in LLM-generated HDL designs.The input to the proposed framework is a C/C++ program that specifies the target circuit's functionality. The program is provided to an LLM to directly generate an HDL design, whose syntax errors are repaired using a Retrieval-Augmented Generation (RAG) mechanism. The functional correctness of the LLM-generated circuit is iteratively improved by comparing its simulated behavior with an HLS reference design produced by conventional HLS tools, which ensures the functional correctness of the result but can lead to suboptimal area and power efficiency. Experimental results demonstrate that circuits generated by the proposed framework achieve significantly better area and power efficiency than conventional HLS designs and approach the quality of human-engineered circuits. Meanwhile, the correctness of the resulting HDL implementation is maintained, highlighting the effectiveness and potential of agentic HDL design leveraging the generative capabilities of LLMs and the rigor of traditional correctness-driven IC design flows.

Problem

• Correcting functional errors in LLM-generated HDL designs
• Improving area and power efficiency compared to HLS designs
• Ensuring functional correctness while maintaining design quality

Innovation

• Uses HLS as functional reference for LLM-generated HDL
• Employs RAG mechanism to repair syntax errors
• Iteratively improves correctness via simulation-HLS comparison