Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond

2025-11-19

AI Summary

RISC-V lags behind proprietary architectures in HPC and AI performance. Method: This paper proposes a fully open-source, chiplet-based evolution path spanning from RTL design to EDA toolchains. It develops a scalable open chiplet architecture family (Occamy → Ogopogo), featuring dual- or quad-chiplet heterogeneous integration interconnected via a mesh NoC, fabricated in 12nm/7nm FinFET processes. Concurrently, it advances open-source simulation platforms, standardized EDA flows, open PDKs, and off-die PHY interfaces. Contribution/Results: We successfully tape-out the 12nm dual-chiplet multicore chip Occamy and complete the 7nm quad-chiplet Ogopogo design—achieving industry-leading compute density. This work constitutes the first systematic validation of open-source chiplets in high-performance RISC-V systems, demonstrating both feasibility and scalability. It establishes a comprehensive, end-to-end technical paradigm for open hardware ecosystems, bridging architectural innovation with practical silicon implementation.

Technology Category

• Machine Learning: Hardware-aware ML
• Humans and AI: Other Foundations of Human Computation & AI
• Cognitive Modeling & Cognitive Systems: Agent Architectures

Application Category

• Economics, Online Markets and Human Computation: Architectures and workflows that use LLMs for crowd work
• Systems and Infrastructure for Web, Mobile and WoT: Experiences and lessons learnt from Web-based algorithms and system deployments
• Security and Privacy: Data transparency and provenance

Abstract

We present a roadmap for open-source chiplet-based RISC-V systems targeting high-performance computing and artificial intelligence, aiming to close the performance gap to proprietary designs. Starting with Occamy, the first open, silicon-proven dual-chiplet RISC-V manycore in 12nm FinFET, we scale to Ramora, a mesh-NoC-based dual-chiplet system, and to Ogopogo, a 7nm quad-chiplet concept architecture achieving state-of-the-art compute density. Finally, we explore possible avenues to extend openness beyond logic-core RTL into simulation, EDA, PDKs, and off-die PHYs.

Problem

• Developing open-source chiplet systems for high-performance computing and AI applications
• Closing performance gaps between open-source and proprietary chiplet designs
• Extending openness beyond logic cores to simulation tools and physical design

Innovation

• Open-source RISC-V chiplets for HPC and AI
• Silicon-proven dual-chiplet manycore in 12nm FinFET
• Quad-chiplet architecture with state-of-the-art compute density