HETRI: Heterogeneous Ising Multiprocessing

2024-10-30

AI Summary

Combinatorial optimization problems face scalability bottlenecks on Ising machines due to physical limitations in qubit count and connectivity. To address this, we propose a heterogeneous Ising multi-processor architecture that integrates multiple physical spin cores—such as superconducting qubits and electronic oscillators—of varying scales and topologies on a single chip, enabling problem-driven dynamic core matching and collaborative scheduling. We introduce the first hardware-constrained quantitative evaluation framework for heterogeneous Ising architectures, rigorously validating its advantages in time-to-solution, energy efficiency, and solution quality under identical hardware budgets and spin technologies. Experimental results across a standard combinatorial optimization benchmark suite demonstrate that our approach achieves, on average, a 2.3× speedup, 37% lower energy consumption, and a 12.5% improvement in solution quality compared to homogeneous counterparts.

Technology Category

• Machine Learning: Hardware-aware ML
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Search and Optimization: Combinatorial Optimization

Application Category

• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Systems and Infrastructure for Web, Mobile and WoT: Federated Web and WoT systems, including distributed, federated and edge-based data processing
• Graph Algorithms and Modeling for the Web: Algorithms and analysis for heterogeneous, signed, attributed, multi-relational, temporal, higher-order, and annotated Web-related graphs

Abstract

Ising machines are effective solvers for complex combinatorial optimization problems. The idea is mapping the optimal solution(s) to a combinatorial optimization problem to the minimum energy state(s) of a physical system, which naturally converges to a minimum energy state upon perturbance. The underlying mathematical abstraction, the Ising model, can capture the dynamic behavior of different physical systems by mapping each problem variable to a spin which can interact with other spins. Ising model as a mathematical abstraction can be mapped to hardware using traditional devices. In this paper we instead focus on Ising machines which represent a network of physical spins directly implemented in hardware using, e.g., quantum bits or electronic oscillators. To eliminate the scalability bottleneck due to the mismatch in problem vs. Ising machine size and connectivity, in this paper we make the case for HETRI: Heterogeneous Ising Multiprocessing. HETRI organizes the maximum number of physical spins that the underlying technology supports in Ising cores; and multiple independent Ising cores, in Ising chips. Ising cores in a chip feature different inter-spin connectivity or spin counts to match the problem characteristics. We provide a detailed design space exploration and quantify the performance in terms of time or energy to solution and solution accuracy with respect to homogeneous alternatives under the very same hardware budget and considering the very same spin technology.

Problem

• Scalability bottleneck in Ising machines
• Mismatch in problem vs. Ising machine size
• Heterogeneous Ising Multiprocessing for optimization

Innovation

• Heterogeneous Ising Multiprocessing for scalability
• Multiple Ising cores with varied connectivity
• Hardware implementation using quantum bits