GraCo - A Graph Composer for Integrated Circuits

2024-11-21

arXiv.org

AI Summary

To address the low efficiency, lack of structural priors, and insufficient constraint enforcement in automated integrated circuit (IC) topology generation, this paper proposes GraCo, a reinforcement learning–based graph construction framework. GraCo formulates circuit synthesis as a constrained graph-structured sequential decision-making process for the first time, integrating graph neural network–based representation learning with SPICE simulation feedback, while enabling explicit incorporation of domain knowledge and enforcing physical consistency constraints. In standard-cell design tasks, GraCo significantly improves sampling efficiency: inverter design is five times faster than random search, and NAND2 gate synthesis achieves 100% success rate with 60% reduction in runtime. This work establishes a novel, interpretable, constraint-aware, and high-efficiency paradigm for AI-driven circuit-level electronic design automation (EDA).

Technology Category

• Machine Learning: Probabilistic Circuits and Graphical Models
• Constraint Satisfaction and Optimization: Constraint Learning and Acquisition
• Search and Optimization: Sampling/Simulation-based Search

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking

Abstract

Designing integrated circuits involves substantial complexity, posing challenges in revealing its potential applications - from custom digital cells to analog circuits. Despite extensive research over the past decades in building versatile and automated frameworks, there remains open room to explore more computationally efficient AI-based solutions. This paper introduces the graph composer GraCo, a novel method for synthesizing integrated circuits using reinforcement learning (RL). GraCo learns to construct a graph step-by-step, which is then converted into a netlist and simulated with SPICE. We demonstrate that GraCo is highly configurable, enabling the incorporation of prior design knowledge into the framework. We formalize how this prior knowledge can be utilized and, in particular, show that applying consistency checks enhances the efficiency of the sampling process. To evaluate its performance, we compare GraCo to a random baseline, which is known to perform well for smaller design space problems. We demonstrate that GraCo can discover circuits for tasks such as generating standard cells, including the inverter and the two-input NAND (NAND2) gate. Compared to a random baseline, GraCo requires 5x fewer sampling steps to design an inverter and successfully synthesizes a NAND2 gate that is 2.5x faster.

Problem

• Develops GraCo for efficient AI-based IC design.
• Uses reinforcement learning to synthesize circuit graphs.
• Enhances sampling efficiency with prior design knowledge.

Innovation

• GraCo uses reinforcement learning for circuit synthesis
• Converts constructed graphs into netlists for SPICE simulation
• Incorporates prior design knowledge to enhance efficiency