An Event-Driven Spiking Compute-In-Memory Macro based on SOT-MRAM

2025-11-05

AI Summary

Existing MRAM-based compute-in-memory (CIM) architectures suffer from low energy efficiency due to reliance on complex analog computing circuits. To address this, this work proposes an event-driven pulse-domain computing architecture built upon spin-orbit torque MRAM (SOT-MRAM). It employs lightweight pulse coding for matrix-vector multiplication, eliminating conventional analog compute units. A novel hybrid serial-parallel memory cell structure and an event-driven computing paradigm enable sparse pulse-domain computation directly within the SOT-MRAM crossbar array. Implemented in 28 nm CMOS technology, the architecture achieves a peak energy efficiency of 243.6 TOPS/W—1.8× to 3.5× higher than state-of-the-art analog and digital CIM approaches. This design breaks through the energy-efficiency bottleneck in CIM systems and establishes a new paradigm for high-efficiency edge AI acceleration.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Search and Optimization: Mixed Discrete/Continuous Search

Application Category

• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• Economics, Online Markets and Human Computation: Architectures and workflows that use LLMs for crowd work

Abstract

The application of Magnetic Random-Access Memory (MRAM) in computing-in-memory (CIM) has gained significant attention. However, existing designs often suffer from high energy consumption due to their reliance on complex analog circuits for computation. In this work, we present a Spin-Orbit- Torque MRAM(SOT-MRAM)-based CIM macro that employs an event-driven spiking processing for high energy efficiency. The SOT-MRAM crossbar adopts a hybrid series-parallel cell structure to efficiently support matrix-vector multiplication (MVM). Signal information is (en) decoded as spikes using lightweight circuits, eliminating the need for conventional area- and powerintensive analog circuits. The SOT-MRAM macro is designed and evaluated in 28nm technology, and experimental results show that it achieves a peak energy efficiency of 243.6 TOPS/W, significantly outperforming existing designs.

Problem

• Reducing energy consumption in MRAM-based computing-in-memory designs
• Eliminating complex analog circuits for efficient matrix-vector multiplication
• Achieving high energy efficiency with event-driven spiking processing

Innovation

• Event-driven spiking processing for energy efficiency
• Hybrid series-parallel SOT-MRAM cell structure
• Lightweight spike circuits replace analog components