AIM: Software and Hardware Co-design for Architecture-level IR-drop Mitigation in High-performance PIM

2025-06-20

International Symposium on Computer Architecture

AI Summary

High-frequency operation in high-performance SRAM-based processing-in-memory (PIM) chips induces severe IR-drop, and conventional circuit-level mitigation techniques suffer from significant PPA (power, performance, area) trade-offs. Method: This paper proposes an architecture-level hardware-software co-optimization framework: (1) a workload-driven IR-drop quantification model; (2) novel Rtog and HR analytical methods enabling joint LHR/WDS (local hit rate/weight distribution skew) architectural optimization; and (3) an IR-Booster dynamic voltage–frequency scaling unit coupled with HR-aware task mapping. The framework integrates bit-serial dataflow modeling, real-time hardware monitoring, and scheduling optimization. Results: Evaluated on a 7-nm 256-TOPS SRAM-PIM chip, post-layout simulation demonstrates up to 69.2% IR-drop suppression, 2.29× energy efficiency improvement, and 1.152× speedup—substantially outperforming state-of-the-art circuit-level approaches.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Sampling/Simulation-based Search
• Intelligent Robots: Learning & Optimization for ROB

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs

Abstract

SRAM Processing-in-Memory (PIM) has emerged as the most promising implementation for high-performance PIM, delivering superior computing density, energy efficiency, and computational precision. However, the pursuit of higher performance necessitates more complex circuit designs and increased operating frequencies, which exacerbate IR-drop issues. Severe IR-drop can significantly degrade chip performance and even threaten reliability. Conventional circuit-level IR-drop mitigation methods, such as back-end optimizations, are resource-intensive and often compromise power, performance, and area (PPA). To address these challenges, we propose AIM, comprehensive software and hardware co-design for architecture-level IR-drop mitigation in high-performance PIM. Initially, leveraging the bit-serial and in-situ dataflow processing properties of PIM, we introduce Rtog and HR, which establish a direct correlation between PIM workloads and IR-drop. Building on this foundation, we propose LHR and WDS, enabling extensive exploration of architecture-level IR-drop mitigation while maintaining computational accuracy through software optimization. Subsequently, we develop IR-Booster, a dynamic adjustment mechanism that integrates software-level HR information with hardware-based IR-drop monitoring to adapt the V-f pairs of the PIM macro, achieving enhanced energy efficiency and performance. Finally, we propose the HR-aware task mapping method, bridging software and hardware designs to achieve optimal improvement. Post-layout simulation results on a 7nm 256-TOPS PIM chip demonstrate that AIM achieves up to 69.2% IR-drop mitigation, resulting in 2.29 × energy efficiency improvement and 1.152 × speedup.

Problem

• Mitigating IR-drop issues in high-performance Processing-in-Memory SRAM
• Addressing performance degradation and reliability threats from severe IR-drop
• Proposing software-hardware co-design to reduce IR-drop and improve efficiency

Innovation

• Software-hardware co-design for architecture-level IR-drop mitigation
• Dynamic adjustment mechanism integrating software and hardware monitoring
• HR-aware task mapping bridging software and hardware designs