FiCABU: A Fisher-Based, Context-Adaptive Machine Unlearning Processor for Edge AI

2025-11-06

AI Summary

Edge AI devices face dual challenges in machine unlearning: stringent privacy compliance requirements and severe computational resource constraints. This paper proposes FiCABU, a hardware-software co-designed processor enabling precise, retraining-free data unlearning directly on edge devices. Methodologically, FiCABU introduces a backend-first, context-adaptive unlearning mechanism integrated with depth-aware balanced suppression; it leverages Fisher information-guided forgetting localization, a customized RISC-V microarchitecture, optimized GEMM pipelining, and a lightweight IP core. The RTL implementation targets 45 nm CMOS technology and is validated on FPGA. Evaluated on ResNet-18 and ViT, FiCABU achieves forgetting accuracy at the random-guessing level (≈50%), preserves model utility comparable to the SSD baseline, reduces computational cost by up to 87.5%, and consumes only 6.48% of SSD’s energy—thereby breaking critical efficiency–accuracy trade-offs in edge machine unlearning.

Technology Category

• Machine Learning: Learning on the Edge & Model Compression
• Computer Vision: Bias, Fairness & Privacy
• Search and Optimization: Learning to Search

Application Category

• Security and Privacy: Security and privacy of machine learning and AI applications
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications

Abstract

Machine unlearning, driven by privacy regulations and the"right to be forgotten", is increasingly needed at the edge, yet server-centric or retraining-heavy methods are impractical under tight computation and energy budgets. We present FiCABU (Fisher-based Context-Adaptive Balanced Unlearning), a software-hardware co-design that brings unlearning to edge AI processors. FiCABU combines (i) Context-Adaptive Unlearning, which begins edits from back-end layers and halts once the target forgetting is reached, with (ii) Balanced Dampening, which scales dampening strength by depth to preserve retain accuracy. These methods are realized in a full RTL design of a RISC-V edge AI processor that integrates two lightweight IPs for Fisher estimation and dampening into a GEMM-centric streaming pipeline, validated on an FPGA prototype and synthesized in 45 nm for power analysis. Across CIFAR-20 and PinsFaceRecognition with ResNet-18 and ViT, FiCABU achieves random-guess forget accuracy while matching the retraining-free Selective Synaptic Dampening (SSD) baseline on retain accuracy, reducing computation by up to 87.52 percent (ResNet-18) and 71.03 percent (ViT). On the INT8 hardware prototype, FiCABU further improves retain preservation and reduces energy to 6.48 percent (CIFAR-20) and 0.13 percent (PinsFaceRecognition) of the SSD baseline. In sum, FiCABU demonstrates that back-end-first, depth-aware unlearning can be made both practical and efficient for resource-constrained edge AI devices.

Problem

• Enabling machine unlearning for edge AI under tight computation and energy constraints
• Reducing computational overhead of unlearning while maintaining model accuracy
• Implementing efficient software-hardware co-design for resource-constrained edge devices

Innovation

• Fisher-based context-adaptive balanced unlearning for edge AI
• Hardware integrates Fisher estimation and dampening IPs
• Back-end-first depth-aware unlearning reduces computation energy