A virtually connected probabilistic computer as a solver for higher-order, densely connected, or reconfigurable combinatorial optimisation problems

2026-05-07

AI Summary

This work addresses the challenge of degraded solution quality in solving high-order, dense, or reconfigurable combinatorial optimization problems due to physical hardware connectivity constraints. To overcome this limitation, the authors propose a virtual connectivity probabilistic computing architecture leveraging a high-speed photonic quantum random number generator. The approach circumvents the problem-size inflation and performance degradation typically incurred by conventional embedding, sparsification, or quadratization techniques through a virtual connection mechanism. By integrating heuristic optimization with a greedy graph coloring algorithm, the framework enables efficient parallel computation. Evaluated on the task of approximating ground states of Erdős–Rényi spin glass models, the proposed architecture achieves speedups of several orders of magnitude over existing digital annealing units, substantially enhancing both computational efficiency and scalability.

Abstract

Recently, there has been growing interest in unconventional computing as an approach for solving NP-hard problems, by developing dedicated hardware to find solutions more efficiently than conventional CPUs. In many of these approaches, however, certain problem geometries must be transformed into forms that are more amenable to the available hardware topology through techniques such as embedding, sparsification, and quadratisation, leading to a deterioration in solution quality. A probabilistic computing architecture based on high speed photonic quantum random number generators was recently proposed which utilises virtual hardware connections (Aboushelbaya et al., 2025), circumventing the necessity for such procedures. Here, we discuss the applicability of virtually connected hardware for running heuristic solving methods to solve a selection of problems, which due to their geometry, would suffer from topological hardware restrictions. We also employ greedy graph colouring algorithms for hardware parallelisation, allowing favourable scaling for desirable solution qualities. To emphasise the difficulty in solving these problems on physically connected hardware, we demonstrate the increase in problem size that would occur with quadratisation or sparsification. Using simulations to emulate hardware, we predict that a photonic probabilistic computer would outperform the time to solution recently reported for digital annealing units, on the ground state approximation of Erdos-Renyi graph spin-glasses, by orders of magnitude.

Problem

• combinatorial optimisation
• NP-hard problems
• hardware topology
• quadratisation
• sparsification

Innovation

• probabilistic computing
• virtual connections
• combinatorial optimization
• photonic hardware
• graph sparsification