LLM-Driven Design Space Exploration of FPGA-based Accelerators

2026-05-07

AI Summary

This work addresses the challenge of manual, expert-dependent tuning in FPGA accelerator design, which involves navigating a vast and complex design space to optimize architecture parameters, dataflow, and memory hierarchy. To automate and accelerate this process, the authors propose SECDA-DSE, a novel design space exploration framework that integrates retrieval-augmented generation (RAG) and chain-of-thought (CoT) prompting with large language models (LLMs). The system combines structured configuration generation, SystemC simulation, and high-level synthesis, and incorporates a feedback loop to reinforce fine-tune the LLM. Evaluated on the Zynq-7000 platform, SECDA-DSE efficiently generates feasible accelerator designs that meet timing and resource constraints, demonstrating significantly improved automation and exploration efficiency while validating the effectiveness of the proposed approach.

Abstract

Designing field-programmable gate array (FPGA)-based accelerators for modern artificial intelligence workloads requires navigating a large and complex hardware design space encompassing architectural parameters, dataflow strategies, and memory hierarchies, making the process time-consuming and resource-intensive. While the SECDA methodology enables rapid hardware-software co-design of accelerators through SystemC simulation and FPGA execution, identifying optimal accelerator configurations still requires substantial manual effort and domain expertise. This work presents SECDA-DSE, a framework that integrates Large Language Models (LLMs) into the SECDA ecosystem, comprising tools built around SECDA to automate the design space exploration (DSE) of FPGA-based accelerators. SECDA-DSE combines a structured DSE Explorer for generating accelerator configurations with an LLM Stack that performs reasoning-guided exploration using retrieval-augmented generation and chain-of-thought prompting, alongside a feedback loop that enables reinforced fine-tuning for continuous improvement. We demonstrate the feasibility of SECDA-DSE through an initial high-level synthesis based evaluation of a generated accelerator design that meets synthesis timing and resource constraints on an Zynq-7000 FPGA.

Problem

• FPGA-based accelerators
• design space exploration
• artificial intelligence workloads
• hardware design space
• accelerator configuration

Innovation

• Large Language Models
• Design Space Exploration
• FPGA-based Accelerators
• Retrieval-Augmented Generation
• Chain-of-Thought Prompting