DICE: Enabling Efficient General-Purpose SIMT Execution with Statically Scheduled Coarse-Grained Reconfigurable Arrays

2026-05-06

AI Summary

This work addresses the high energy consumption of traditional GPUs under the SIMT programming model, which stems from frequent register file accesses and complex control logic. The authors propose replacing the SIMD backend with a statically scheduled coarse-grained reconfigurable array (CGRA) that pipelines active threads and enables direct data transfer among processing elements, drastically reducing intermediate value accesses to registers. A novel p-graph program representation is introduced to decouple dynamic dependency edges, and in conjunction with double-buffered configuration memory, compile-time graph unrolling, and a temporal memory coalescing unit (TMCU), the design efficiently supports dynamic behavior while retaining static scheduling. Experimental results on the Rodinia benchmark suite show an average 68% reduction in register file accesses, 1.77–1.90× improvement in dynamic energy efficiency, 42.0%–45.9% lower power consumption, and performance comparable to that of NVIDIA Turing GPUs.

Abstract

While GPUs dominate massively parallel computing through the single-instruction, multiple-thread (SIMT) programming model, their underlying single-instruction, multiple-data (SIMD) execution incurs substantial energy overhead from frequent register file (RF) accesses and complex control logic. We present DICE, a novel architecture that addresses these inefficiencies by replacing the SIMD backend with minimal-overhead, statically scheduled coarse-grained reconfigurable arrays (CGRAs). Unlike SIMD units that execute warps of threads in lockstep, DICE dispatches active threads in a pipelined manner onto the CGRA fabric, where data flow directly between processing elements (PEs), reducing RF accesses for intermediate values. To handle operations with runtime dynamism, such as variable-latency memory loads and data-dependent control flow, while preserving static scheduling, DICE compiles programs into "p-graphs" by partitioning dynamic dependence edges across separate CGRA configurations. DICE further introduces several key optimizations: double-buffered configuration memory to hide reconfiguration latency, compile-time p-graph unrolling to enhance resource utilization, and a temporal memory coalescing unit (TMCU) to merge memory requests from consecutive, pipelined threads. Evaluations on Rodinia benchmarks in Accel-sim demonstrate that DICE reduces register file accesses by 68% on average. With equivalent computation and memory resources, DICE's CGRA Processors (CPs) achieve a geometric mean of 1.77-1.90x dynamic energy efficiency and 42.0%-45.9% average power reduction compared to the modeled NVIDIA Turing Streaming Multiprocessors (SMs), while the full DICE system achieves performance comparable to the modeled Turing GPU baselines. DICE demonstrates that spatial pipeline execution can deliver substantial energy savings without sacrificing performance.

Problem

• SIMT
• SIMD
• energy overhead
• register file accesses
• coarse-grained reconfigurable arrays

Innovation

• Coarse-Grained Reconfigurable Array
• SIMT Execution
• Static Scheduling
• Spatial Pipeline
• Energy Efficiency