ReQISC: A Reconfigurable Quantum Computer Microarchitecture and Compiler Co-Design
🤖 AI Summary
Current quantum hardware is constrained by fixed, low-expressivity native gate sets (e.g., CNOT/CZ), resulting in deep circuits, low fidelity, and high calibration overhead—hindering practical deployment of expressive quantum instruction set architectures (ISAs). Method: We propose ReQISC, a reconfigurable quantum microarchitecture that enables direct, efficient hardware support for arbitrary two-qubit gates equivalent to SU(4), and develop an end-to-end SU(4)-aware compilation framework integrating pulse-level optimization, program-aware qubit mapping, dynamic calibration, and transparent routing. Contribution/Results: Compared to conventional approaches, ReQISC reduces average two-qubit gate pulse duration by 4.97×, significantly lowering circuit depth, mapping overhead, and fidelity degradation. This advances high-expressivity quantum ISAs from theoretical concept toward practical realization.
Application Category
📝 Abstract
The performance of current quantum hardware is severely limited. While expanding the quantum ISA with high-fidelity, expressive basis gates is a key path forward, it imposes significant gate calibration overhead and complicates compiler optimization. As a result, even though more powerful ISAs have been designed, their use remains largely conceptual rather than practical. To move beyond these hurdles, we introduce the concept of"reconfigurable quantum instruction set computers"(ReQISC), which incorporates: (1) a unified microarchitecture capable of directly implementing arbitrary 2Q gates equivalently, i.e., SU(4) modulo 1Q rotations, with theoretically optimal gate durations given any 2Q coupling Hamiltonians; (2) a compilation framework tailored to ReQISC primitives for end-to-end synthesis and optimization, comprising a program-aware pass that refines high-level representations, a program-agnostic pass for aggressive circuit-level optimization, and an SU(4)-aware routing pass that minimizes hardware mapping overhead. We detail the hardware implementation to demonstrate the feasibility, in terms of both pulse control and calibration of this superior gate scheme on realistic hardware. By leveraging the expressivity of SU(4) and the time minimality realized by the underlying microarchitecture, the SU(4)-based ISA achieves remarkable performance, with a 4.97-fold reduction in average pulse duration to implement arbitrary 2Q gates, compared to the usual CNOT/CZ scheme on mainstream flux-tunable transmons. Supported by the end-to-end compiler, ReQISC outperforms the conventional CNOT-ISA, SOTA compiler, and pulse implementation counterparts, in significantly reducing 2Q gate counts, circuit depth, pulse duration, qubit mapping overhead, and program fidelity losses. For the first time, ReQISC makes the theoretical benefits of continuous ISAs practically feasible.
Problem
Research questions and friction points this paper is trying to address.
Overcoming quantum hardware limitations through reconfigurable microarchitecture and compiler co-design
Reducing gate calibration overhead while enabling expressive quantum instruction sets
Optimizing circuit implementation with SU(4)-aware compilation and minimal pulse durations
Innovation
Methods, ideas, or system contributions that make the work stand out.
Unified microarchitecture implementing arbitrary two-qubit gates
Compilation framework with program-aware and agnostic optimization
SU(4)-aware routing minimizing hardware mapping overhead
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