DRACO: Co-design for DSP-Efficient Rigid Body Dynamics Accelerator

2025-11-11

AI Summary

Real-time rigid-body dynamics (RBD) computation for high-degree-of-freedom (DOF) robots imposes excessive demands on digital signal processor (DSP) resources, while simultaneously compromising accuracy and scalability. To address this, this paper proposes a hardware-efficient FPGA accelerator architecture. Our method introduces three key innovations: (1) an accuracy-aware quantization framework that systematically models and evaluates the impact of quantization error on closed-loop control performance—first of its kind; (2) a latency-sensitive recursive reciprocal optimization combined with decoupled mass matrix inversion; and (3) a module-level dynamic DSP reuse mechanism. Implemented on a Xilinx UltraScale+ FPGA, the accelerator achieves up to 8× higher throughput and 7.4× lower end-to-end latency compared to CPU/GPU baselines. These improvements significantly enhance real-time capability, energy efficiency, and scalability for high-DOF robotic systems.

Technology Category

• Machine Learning: Hardware-aware ML
• Intelligent Robots: Learning & Optimization for ROB
• Cognitive Modeling & Cognitive Systems: Agent Architectures

Application Category

• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Responsible Web: Machine-in-the-loop, human agency and autonomy
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs

Abstract

We propose a hardware-efficient RBD accelerator based on FPGA, introducing three key innovations. First, we propose a precision-aware quantization framework that reduces DSP demand while preserving motion accuracy. This is also the first study to systematically evaluate quantization impact on robot control and motion for hardware acceleration. Second, we leverage a division deferring optimization in mass matrix inversion algorithm, which decouples reciprocal operations from the longest latency path to improve the performance. Finally, we present an inter-module DSP reuse methodology to improve DSP utilization and save DSP usage. Experiment results show that our work achieves up to 8x throughput improvement and 7.4x latency reduction over state-of-the-art RBD accelerators across various robot types, demonstrating its effectiveness and scalability for high-DOF robotic systems.

Problem

• Reduces DSP demand while preserving motion accuracy through quantization
• Improves performance by decoupling reciprocal operations from critical paths
• Enhances DSP utilization via inter-module reuse methodology

Innovation

• Precision-aware quantization framework reduces DSP demand
• Division deferring optimization improves mass matrix inversion
• Inter-module DSP reuse methodology enhances utilization