Hardware-Compatible Single-Shot Feasible-Space Heuristics for Solving the Quadratic Assignment Problem

2025-03-12

AI Summary

This work addresses the Quadratic Assignment Problem (QAP)—a canonical constrained combinatorial optimization problem—when solved on specialized hardware such as memristor-based in-memory Ising machines. Key challenges include high overhead from QUBO reformulation, limited parallelism, and difficulty ensuring solution feasibility. To overcome these, we propose a hardware-friendly, single-pass feasible-domain heuristic algorithm. Our method introduces, for the first time, a fully parallel neighborhood search over feasible solutions—bypassing QUBO encoding entirely and performing structure-aware local search directly in the original constraint space. We further design a binary-constraint-preserving update strategy tailored for in-memory computing and a dedicated interface for memristor architectures. Implemented on CPU, our algorithm matches state-of-the-art heuristics in performance, while its analog-hardware-native design significantly improves solving efficiency and deployment flexibility. This work establishes a scalable hardware–algorithm co-design paradigm for constrained combinatorial optimization.

Technology Category

• Constraint Satisfaction and Optimization: Distributed CSP/Optimization
• Search and Optimization: Mixed Discrete/Continuous Search
• Machine Learning: Hardware-aware ML

Application Category

• Graph Algorithms and Modeling for the Web: Querying, indexing, and retrieval in Web-related graphs
• Search and Retrieval-Augmented AI: Vertical and domain-specific search
• Responsible Web: Human-perceived consequences of algorithmic deployment on the web

Abstract

Research into the development of special-purpose computing architectures designed to solve quadratic unconstrained binary optimization (QUBO) problems has flourished in recent years. It has been demonstrated in the literature that such special-purpose solvers can outperform traditional CMOS architectures by orders of magnitude with respect to timing metrics on synthetic problems. However, they face challenges with constrained problems such as the quadratic assignment problem (QAP), where mapping to binary formulations such as QUBO introduces overhead and limits parallelism. In-memory computing (IMC) devices, such as memristor-based analog Ising machines, offer significant speedups and efficiency gains over traditional CPU-based solvers, particularly for solving combinatorial optimization problems. In this work, we present a novel local search heuristic designed for IMC hardware to tackle the QAP. Our approach enables massive parallelism that allows for computing of full neighbourhoods simultaneously to make update decisions. We ensure binary solutions remain feasible by selecting local moves that lead to neighbouring feasible solutions, leveraging feasible-space search heuristics and the underlying structure of a given problem. Our approach is compatible with both digital computers and analog hardware. We demonstrate its effectiveness in CPU implementations by comparing it with state-of-the-art heuristics for solving the QAP.

Problem

• Develops hardware-compatible heuristics for quadratic assignment problem.
• Addresses challenges in constrained optimization with binary formulations.
• Enables massive parallelism for efficient combinatorial optimization solutions.

Innovation

• In-memory computing for QAP optimization
• Local search heuristic for IMC hardware
• Feasible-space search with massive parallelism