DynamicRTL: RTL Representation Learning for Dynamic Circuit Behavior

2025-11-12

AI Summary

Existing GNN approaches model only the static structural topology of RTL circuits, failing to capture multi-cycle dynamic execution behaviors—thereby limiting circuit verification and optimization performance. To address this, we propose DR-GNN: the first graph neural network that jointly encodes static control-data flow graphs (CDFGs) and dynamic simulation traces to explicitly model operation-level temporal dependencies. We further construct the first large-scale dynamic RTL circuit dataset and enable cross-task transfer learning. Extensive experiments demonstrate that DR-GNN significantly outperforms state-of-the-art methods in branch hit-rate and toggle-rate prediction. Moreover, it exhibits strong generalization capability in power estimation and assertion prediction. By unifying static structure and dynamic behavior in representation learning, DR-GNN establishes a novel paradigm for behavior-aware circuit representation learning.

Technology Category

• Machine Learning: Probabilistic Circuits and Graphical Models
• Knowledge Representation and Reasoning: Geometric, Spatial, and Temporal Reasoning
• Planning, Routing, and Scheduling: Activity and Plan Recognition

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs

Abstract

There is a growing body of work on using Graph Neural Networks (GNNs) to learn representations of circuits, focusing primarily on their static characteristics. However, these models fail to capture circuit runtime behavior, which is crucial for tasks like circuit verification and optimization. To address this limitation, we introduce DR-GNN (DynamicRTL-GNN), a novel approach that learns RTL circuit representations by incorporating both static structures and multi-cycle execution behaviors. DR-GNN leverages an operator-level Control Data Flow Graph (CDFG) to represent Register Transfer Level (RTL) circuits, enabling the model to capture dynamic dependencies and runtime execution. To train and evaluate DR-GNN, we build the first comprehensive dynamic circuit dataset, comprising over 6,300 Verilog designs and 63,000 simulation traces. Our results demonstrate that DR-GNN outperforms existing models in branch hit prediction and toggle rate prediction. Furthermore, its learned representations transfer effectively to related dynamic circuit tasks, achieving strong performance in power estimation and assertion prediction.

Problem

• Capturing dynamic circuit behavior beyond static characteristics
• Learning RTL representations with multi-cycle execution patterns
• Addressing circuit verification and optimization through dynamic dependencies

Innovation

• DR-GNN integrates static structures with multi-cycle execution behaviors
• Uses operator-level CDFG to capture dynamic dependencies and runtime execution
• Leverages comprehensive dataset with Verilog designs and simulation traces