History-Aware Trajectory k-Anonymization Using an FPGA-Based Hardware Accelerator for Real-Time Location Services

2025-11-12

AI Summary

Existing FPGA-based trajectory k-anonymization methods rely solely on shortest-path modeling, neglecting realistic mobility patterns and thus yielding anonymized trajectories with low utility. This paper proposes a history-aware real-time trajectory anonymization framework. We introduce, for the first time, a historical trajectory weighting mechanism that fuses parallel historical path search with shortest-path computation; a fixed-point frequency counting module dynamically estimates path traversal frequencies to prioritize preservation of high-frequency, empirically observed routes. We design a custom FPGA hardware architecture integrating parallel search, historical matching, and weighted computation units to achieve low-latency, high-throughput processing. Our system achieves a throughput of over 6,000 trajectories per second, improves data retention rate by 1.2% over baseline approaches, and significantly enhances fidelity on major roads and behavioral consistency with real-world mobility patterns.

Technology Category

• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems
• Machine Learning: Hardware-aware ML
• Search and Optimization: Sampling/Simulation-based Search

Application Category

• Security and Privacy: Tracking, profiling, and countermeasures against them
• Graph Algorithms and Modeling for the Web: Efficient manipulation of static and dynamic Web-related graphs
• User Modeling, Personalization and Recommendation: User privacy protection in personalized systems

Abstract

Our previous work established the feasibility of FPGA-based real-time trajectory anonymization, a critical task for protecting user privacy in modern location-based services (LBS). However, that pioneering approach relied exclusively on shortest-path computations, which can fail to capture re- alistic travel behavior and thus reduce the utility of the anonymized data. To address this limitation, this paper introduces a novel, history-aware trajectory k-anonymization methodology and presents an advanced FPGA-based hardware architecture to implement it. Our proposed architecture uniquely integrates par- allel history-based trajectory searches with conventional shortest- path finding, using a custom fixed-point counting module to ac- curately weigh contributions from historical data. This approach enables the system to prioritize behaviorally common routes over geometrically shorter but less-traveled paths. The FPGA implementation demonstrates that our new architecture achieves a real-time throughput of over 6,000 records/s, improves data retention by up to 1.2% compared to our previous shortest-path- only design, and preserves major arterial roads more effectively. These results signify a key advancement, enabling high-fidelity, history-aware anonymization that preserves both privacy and behavioral accuracy under the strict latency constraints of LBS.

Problem

• Enhancing trajectory anonymization by incorporating historical travel behavior data
• Overcoming limitations of shortest-path methods for realistic route preservation
• Achieving real-time privacy protection while maintaining behavioral accuracy

Innovation

• History-aware trajectory k-anonymization methodology
• FPGA-based hardware architecture with parallel searches
• Custom fixed-point module for historical data weighting