Efficient Hyperdimensional Computing with Modular Composite Representations

📅 2025-11-12
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This work addresses the lack of systematic trade-off analysis and hardware-aware evaluation for Modular Composite Representation (MCR), a hyperdimensional computing model based on high-dimensional integer vectors and modular arithmetic. We conduct the first joint assessment of capacity, precision, and hardware efficiency. Our methodology adopts a hardware-software co-design approach: we formalize MCR operations as synthesizable digital logic primitives, design a dedicated hardware accelerator, and empirically validate it across 123 benchmark datasets. Results demonstrate that, compared to high-precision floating-point models, MCR retains comparable representational capacity while reducing memory footprint by 75%. The hardware-accelerated implementation achieves an average 1000× speedup and 2.68× improvement in energy efficiency. These findings rigorously substantiate MCR’s distinctive advantages—lightweight representation, computational efficiency, and deployability—making it particularly suitable for resource-constrained edge AI applications.

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📝 Abstract
The modular composite representation (MCR) is a computing model that represents information with high-dimensional integer vectors using modular arithmetic. Originally proposed as a generalization of the binary spatter code model, it aims to provide higher representational power while remaining a lighter alternative to models requiring high-precision components. Despite this potential, MCR has received limited attention. Systematic analyses of its trade-offs and comparisons with other models are lacking, sustaining the perception that its added complexity outweighs the improved expressivity. In this work, we revisit MCR by presenting its first extensive evaluation, demonstrating that it achieves a unique balance of capacity, accuracy, and hardware efficiency. Experiments measuring capacity demonstrate that MCR outperforms binary and integer vectors while approaching complex-valued representations at a fraction of their memory footprint. Evaluation on 123 datasets confirms consistent accuracy gains and shows that MCR can match the performance of binary spatter codes using up to 4x less memory. We investigate the hardware realization of MCR by showing that it maps naturally to digital logic and by designing the first dedicated accelerator. Evaluations on basic operations and 7 selected datasets demonstrate a speedup of up to 3 orders of magnitude and significant energy reductions compared to software implementation. When matched for accuracy against binary spatter codes, MCR achieves on average 3.08x faster execution and 2.68x lower energy consumption. These findings demonstrate that, although MCR requires more sophisticated operations than binary spatter codes, its modular arithmetic and higher per-component precision enable lower dimensionality. When realized with dedicated hardware, this results in a faster, more energy-efficient, and high-precision alternative to existing models.
Problem

Research questions and friction points this paper is trying to address.

Evaluating modular composite representations for hyperdimensional computing trade-offs
Comparing MCR capacity and accuracy against existing computing models
Designing hardware accelerator to demonstrate MCR efficiency gains
Innovation

Methods, ideas, or system contributions that make the work stand out.

Uses high-dimensional integer vectors with modular arithmetic
Achieves balance between capacity, accuracy, and hardware efficiency
Enables lower dimensionality through modular arithmetic operations
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