Simulation-Driven Evaluation of Chiplet-Based Architectures Using VisualSim

2025-11-03

AI Summary

Facing bottlenecks in cost, energy efficiency, and scalability inherent to monolithic chips, chiplet-based architectures demand high-fidelity system-level performance evaluation methods. This paper proposes a VisualSim-based simulation framework for chiplet architecture exploration, instantiated with a multi-core ARM cluster and the CMN600 NoC. It models critical behaviors including inter-chip communication, memory access patterns, workload distribution, and power-performance trade-offs. The framework enables quantitative analysis under complex workloads and, for the first time, systematically reveals that inter-chip interconnect latency and task scheduling co-design dominantly govern overall energy efficiency and scalability. Experimental results demonstrate that the method accurately identifies performance bottlenecks, improving analytical accuracy and design iteration efficiency over conventional evaluation approaches. It establishes a reusable simulation paradigm and theoretical foundation for chiplet system architecture exploration and optimization.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Sampling/Simulation-based Search
• Cognitive Modeling & Cognitive Systems: (Computational) Cognitive Architectures

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Web Mining and Content Analysis: Web data generation and simulation
• Economics, Online Markets and Human Computation: Cost models of using LLMs in production systems

Abstract

This paper focuses on the simulation of multi-die System-on-Chip (SoC) architectures using VisualSim, emphasiz- ing chiplet-based system modeling and performance analysis. Chiplet technology presents a promising alternative to traditional monolithic chips, which face increasing challenges in manufactur- ing costs, power efficiency, and performance scaling. By integrat- ing multiple small modular silicon units into a single package, chiplet-based architectures offer greater flexibility and scalability at a lower overall cost. In this study, we developed a detailed sim- ulation model of a chiplet-based system, incorporating multicore ARM processor clusters interconnected through a ARM CMN600 network-on-chip (NoC) for efficient communication [4], [7]. The simulation framework in VisualSim enables the evaluation of critical system metrics, including inter-chiplet communication latency, memory access efficiency, workload distribution, and the power-performance tradeoff under various workloads. Through simulation-driven insights, this research highlights key factors influencing chiplet system performance and provides a foundation for optimizing future chiplet-based semiconductor designs.

Problem

• Simulating multi-die chiplet architectures for performance analysis
• Evaluating communication latency and power-performance tradeoffs
• Optimizing chiplet-based system designs through simulation insights

Innovation

• Simulation-driven chiplet architecture evaluation using VisualSim
• Modeled multicore ARM clusters with CMN600 NoC
• Analyzed communication latency and power-performance tradeoffs