Self-Heating and Parasitic Effects in Multi-Tier CFET Design

2026-03-23

AI Summary

This study addresses the impact of self-heating and middle-of-line/back-end-of-line (MOL/BEOL) parasitic effects on device performance in multilayer stacked complementary FETs (CFETs). For the first time, it systematically quantifies the exacerbated temperature rise in a four-layer CFET structure due to increased thermal resistance from the substrate—reaching 83.5 K for nFETs and 98.5 K for pFETs—and a significant increase in parasitic RC, with the top layer exhibiting 10× and 6.5× higher values compared to a two-layer counterpart. Using experimentally calibrated 3D TCAD simulations integrated with a full interconnect model, the parasitic network is extracted and thermal distributions analyzed. Despite heightened parasitics, the four-layer CFET inverter exhibits only an 8.2%–10% delay increase, markedly outperforming the 37.25% delay penalty of the two-layer structure, thereby revealing its superior performance potential and unique delay mechanisms at high integration densities.

Technology Category

• Machine Learning: Hardware-aware ML
• Data Mining & Knowledge Management: Scalability, Parallel & Distributed Systems
• Computer Vision: Multi-modal Vision

Application Category

• Systems and Infrastructure for Web, Mobile and WoT: Web performance, measurement, and characterization
• Graph Algorithms and Modeling for the Web: Algorithms and analysis for heterogeneous, signed, attributed, multi-relational, temporal, higher-order, and annotated Web-related graphs
• Security and Privacy: Large-scale security measurements

Abstract

In this article, we study the impact of self-heating effects (SHEs) and middle of line (MOL) and back-end of line (BEOL) induced parasitics on multi-tier CFET design, where multiple nanosheet devices are vertically stacked. We analyze and compare the 4-tier CFET design with the conventional 2-tier CFET, using TCAD models calibrated to experimental measurements. Additionally, TCAD simulations are used to model and analyze SHE-induced heat distribution and temperature profiles and to extract the detailed parasitic RC network from 3D models of CMOS inverters designed with full MOL and BEOL interconnects. At the device level, the maximum temperature rise (TMAX) caused by SHE in nFET and pFET devices of the 2-tier CFET architecture is 62 K and 74 K, respectively. Due to the increased distance from the substrate heat sink, the upper-tier nFET and pFET devices in the 4-tier design show higher TMAX of 83.5 K and 98.5 K and more heat trapping in the stacked layers. Furthermore, in the 4-tier CFET-based CMOS inverters, the BEOL-induced parasitic RCs are, respectively, 10 and 6.5 times higher in the top-tier than in the 2-tier CFET-based inverters. In the bottom tier, the corresponding parasitic RC elements are 6.26 and 2 times higher, respectively, than in the 2-tier inverters. Finally, compared to the 4-tier design without parasitics, the propagation delay of the top and bottom tier inverters increases by 10% and 8.2%, respectively, due to the interconnect parasitic RCs. For the conventional 2-tier inverter, the corresponding degradation of delay with parasitic RCs is 37.25%.

Problem

• self-heating effects
• parasitic effects
• multi-tier CFET
• BEOL parasitics
• thermal management

Innovation

• CFET
• self-heating effects
• parasitic RC
• multi-tier stacking
• TCAD simulation