Algorithm and Hardware Co-Design for Efficient Complex-Valued Uncertainty Estimation

2026-04-21

AI Summary

This work addresses the limitations of existing complex-valued neural networks, which struggle to quantify predictive uncertainty and lack hardware-efficient designs. We propose BayesCVNN, the first Bayesian complex-valued neural network capable of uncertainty quantification, and introduce novel configuration spaces—layer-wise and partial mixing—to enable automated architecture search that jointly optimizes real and imaginary components. Furthermore, we develop a modular FPGA-oriented acceleration framework to achieve algorithm-hardware co-optimization. Experiments demonstrate that the automatically searched architectures outperform handcrafted models in both accuracy and hardware efficiency. The resulting FPGA accelerator achieves 4.5–13× speedup over GPU implementations while consuming less than 10% of the power, significantly advancing the state of the art at both algorithmic and hardware levels.

Technology Category

• Computer Vision: Learning & Optimization for CV
• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems

Abstract

Complex-Valued Neural Networks (CVNNs) have significant advantages in handling tasks that involve complex numbers. However, existing CVNNs are unable to quantify predictive uncertainty. We propose, for the first time, dropout-based Bayesian Complex-Valued Neural Networks (BayesCVNNs) to enable uncertainty quantification for complex-valued applications, exhibiting broad applicability and efficiency for hardware implementation due to modularity. Furthermore, as the dual-part nature of complex values significantly broadens the design space and enables novel configurations based on layer-mixing and part-mixing, we introduce an automated search approach to effectively identify optimal configurations for both real and imaginary components. To facilitate deployment, we present a framework that generates customized FPGA-based accelerators for BayesCVNNs, leveraging a set of optimized building blocks. Experiments demonstrate the best configuration can be effectively found via the automated search, attaining higher performance with lower hardware costs compared with manually crafted models. The optimized accelerators achieve approximately 4.5x and 13x speedups on different models with less than 10% power consumption compared to GPU implementations, and outperform existing work in both algorithm and hardware aspects. Our code is publicly available at: https://github.com/zehuanzhang/BayesCVNN.git.

Problem

• Complex-Valued Neural Networks
• Uncertainty Estimation
• Bayesian Neural Networks
• Hardware Acceleration
• FPGA

Innovation

• Bayesian Complex-Valued Neural Networks
• Uncertainty Quantification
• Algorithm-Hardware Co-Design
• Automated Architecture Search
• FPGA Acceleration