Toward designing workload-aware Surface Code Architectures

2026-04-21

AI Summary

This work addresses the challenge in fault-tolerant quantum computing of simultaneously achieving high-density logical qubit layouts and low access latency within conventional surface code architectures. The authors propose a novel surface code architecture centered on ancilla qubits, wherein physical layout is guided by a workload-driven distribution of T-gates and augmented with an on-demand reconfigurable optimization mechanism tailored for Y-basis measurements. This design enables efficient concurrent execution of multiple programs. Compared to baseline approaches, the proposed architecture reduces the number of data blocks by approximately 21%, achieves instruction cycles close to the theoretical optimum, and maintains 90% execution efficiency even when running ten programs concurrently.

Technology Category

• Machine Learning: Quantum Machine Learning
• Search and Optimization: Distributed Search
• Constraint Satisfaction and Optimization: Distributed CSP/Optimization

Application Category

• Security and Privacy: Large-scale security measurements
• Economics, Online Markets and Human Computation: Incentives in network design for Web infrastructures and ecosystems
• Graph Algorithms and Modeling for the Web: Querying, indexing, and retrieval in Web-related graphs

Abstract

Practical quantum advantage is expected to depend on fault-tolerant quantum computing, although the architectural overhead needed to support fault tolerance is still extremely high. Prior FTQC designs generally emphasize either fast logical-qubit accessibility at the cost of significant qubit overhead, or high logical-qubit density at the cost of added workload latency. We propose an architecture that balances these competing objectives by placing surface-code patches around an ancilla-centric region, which yields nearly uniform ancilla access for all data qubits. Building on this design, we introduce a new workload-driven placement method that uses the $T$-gate profile of an application to determine an effective floorplan. We further provide a reconfigurable optimization for reducing the latency of $Y$-gate measurements on a per-workload basis. To improve flexibility, we also study concurrent execution of multiple programs on the same architecture. Numerical evaluation indicates that our approach keeps cycles per instruction near the optimal regime while reducing the number of required data tiles by up to $\sim21\%$, and achieves up to $\sim90\%$ efficiency when running 10 programs concurrently.

Problem

• fault-tolerant quantum computing
• surface code
• workload-aware architecture
• logical qubit placement
• concurrent execution

Innovation

• surface code
• workload-aware architecture
• fault-tolerant quantum computing
• T-gate profiling
• concurrent execution