RejSCore: Rejection Sampling Core for Multivariate-based Public key Cryptography

2025-10-26

AI Summary

Rejection sampling in post-quantum multivariate public-key cryptography (MPKC) signatures suffers from low hardware efficiency and insufficient hardware-oriented optimization, especially on resource-constrained platforms. Method: This paper proposes RejSCore—the first lightweight, domain-specific hardware accelerator tailored for MPKC rejection sampling. It employs an iterative rejection sampling algorithm coupled with an AES-CTR-128 pseudorandom number generator to balance precision and energy efficiency. Contribution/Results: Implemented on an Artix-7 FPGA, RejSCore occupies only 2,042 slices; in 65 nm CMOS, it achieves a compact die area of 464,866 μm² and a maximum operating frequency of 565 MHz. It generates a QR-UOV Level-I signature in just 8,525 clock cycles. Compared to prior designs, RejSCore significantly reduces area and power consumption, yielding substantial improvements in Area-Delay Product (ADP) and Power-Delay Product (PDP). This work provides critical hardware enablers for practical MPKC deployment in embedded systems and IoT applications.

Technology Category

• Machine Learning: Hardware-aware ML
• Search and Optimization: Sampling/Simulation-based Search
• Reasoning under Uncertainty: Stochastic Optimization

Application Category

• Security and Privacy: Large-scale security measurements
• User Modeling, Personalization and Recommendation: Attacks and countermeasures in recommendation systems
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines

Abstract

Post-quantum multivariate public key cryptography (MPKC) schemes resist quantum threats but require heavy operations, such as rejection sampling, which challenge resource-limited devices. Prior hardware designs have addressed various aspects of MPKC signature generation. However, rejection sampling remains largely unexplored in such contexts. This paper presents RejSCore, a lightweight hardware accelerator for rejection sampling in post-quantum cryptography. It specifically targets the QR-UOV scheme, which is a prominent candidate under the second-round of the National Institute of Standards and Technology (NIST) additional digital signature standardization process. The architecture includes an AES-CTR-128-based pseudorandom number generator. Moreover, a lightweight iterative method is employed in rejection sampling, offering reduced resource consumption and area overhead while slightly increasing latency. The performance of RejSCore is comprehensively evaluated on Artix-7 FPGAs and 65 nm CMOS technology using the Area-Delay Product (ADP) and Power-Delay Product (PDP). On Artix-7 and 65 nm CMOS, RejSCore achieves an area of 2042 slices and 464,866~$μm^2$, with operating frequencies of 222 MHz and 565 MHz, respectively. Using the QR-UOV parameters for security level I ($q = 127$, $v = 156$, $m = 54$, $l = 3$), the core completes its operation in 8525 clock cycles. The ADP and PDP evaluations confirm RejSCore's suitability for deployment in resource-constrained and security-critical environments.

Problem

• Accelerating rejection sampling for post-quantum multivariate cryptography
• Addressing hardware inefficiency in QR-UOV signature generation
• Optimizing resource consumption for constrained security devices

Innovation

• Lightweight hardware accelerator for rejection sampling
• AES-CTR-128-based pseudorandom number generator architecture
• Iterative rejection sampling method reduces resource consumption