Approximate Signed Multiplier with Sign-Focused Compressor for Edge Detection Applications

2025-10-26

AI Summary

In signed multiplication for edge detection and similar applications, frequent occurrences of constant-1 terms and negative partial products severely degrade energy efficiency. To address this, we propose a sign-aware approximate signed multiplier architecture. Our method introduces two novel compression units—A+B+C+1 and A+B+C+D+1—that explicitly model sign logic to simplify negative-term handling; it further combines truncation of the least-significant (N−1) columns of the partial-product matrix with an error-compensation mechanism, achieving substantial computational savings under controllable accuracy loss. Integrated into a custom convolutional layer, the proposed multiplier, implemented in 8-bit precision, reduces power-delay product by 29.21% and power consumption by 14.39% over the state-of-the-art. Experimental validation on real-world edge detection tasks confirms its superior trade-off between accuracy and energy efficiency.

Technology Category

• Machine Learning: Hardware-aware ML
• Computer Vision: Multi-modal Vision
• Search and Optimization: Non-convex Optimization

Application Category

• Graph Algorithms and Modeling for the Web: Algorithms and analysis for heterogeneous, signed, attributed, multi-relational, temporal, higher-order, and annotated Web-related graphs
• Search and Retrieval-Augmented AI: Efficiency and scalability of Web search engines
• Security and Privacy: Privacy-enhancing technologies

Abstract

This paper presents an approximate signed multiplier architecture that incorporates a sign-focused compressor, specifically designed for edge detection applications in machine learning and signal processing. The multiplier incorporates two types of sign-focused compressors: A + B + C + 1 and A + B + C + D + 1. Both exact and approximate compressor designs are utilized, with a focus on efficiently handling constant value "1" and negative partial products, which frequently appear in the partial product matrices of signed multipliers. To further enhance efficiency, the lower N - 1 columns of the partial product matrix are truncated, followed by an error compensation mechanism. Experimental results show that the proposed 8-bit approximate multiplier achieves a 29.21% reduction in power delay product (PDP) and a 14.39% reduction in power compared to the best of existing multipliers. The proposed multiplier is integrated into a custom convolution layer and performs edge detection, demonstrating its practical utility in real-world applications.

Problem

• Designing efficient approximate signed multipliers for edge detection applications
• Optimizing power consumption and delay in signed multiplier architectures
• Handling negative partial products and truncation in multiplier designs

Innovation

• Approximate signed multiplier with sign-focused compressor
• Truncates lower columns with error compensation mechanism
• Reduces power delay product by 29.21%