QiMeng-SALV: Signal-Aware Learning for Verilog Code Generation

2025-10-22

AI Summary

Existing RL-based Verilog synthesis methods suffer from sparse and semantically impoverished functional rewards, hindering guaranteed functional correctness of generated code. To address this, we propose a signal-aware learning framework that shifts optimization granularity from the module level to the signal level: leveraging AST analysis and signal-level equivalence checking, we precisely identify and extract correct signal fragments from erroneous modules to construct fine-grained functional rewards; we further design a signal-aware Direct Preference Optimization (DPO) algorithm to explicitly optimize preferences over critical signal behaviors. This approach substantially alleviates reward sparsity and achieves state-of-the-art performance on VerilogEval and RTLLM benchmarks—our 7B-parameter model surpasses the open-source CodeV model trained with comparable resources and matches the performance of the 671B-parameter DeepSeek v3.

Technology Category

• Search and Optimization: Learning to Search
• Natural Language Processing: Code Generation / Program Synthesis from Natural Language
• Intelligent Robots: Learning & Optimization for ROB

Application Category

• Search and Retrieval-Augmented AI: Web learning to rank, online learning, and counterfactual learning for ranking
• Semantics and Knowledge: Methods to enhance, augment, integrate or synergize semantic models such as knowledge graphs and LLMs
• Graph Algorithms and Modeling for the Web: Foundation models and LLMs for Web-related graphs

Abstract

The remarkable progress of Large Language Models (LLMs) presents promising opportunities for Verilog code generation which is significantly important for automated circuit design. The lacking of meaningful functional rewards hinders the preference optimization based on Reinforcement Learning (RL) for producing functionally correct Verilog code. In this paper, we propose Signal-Aware Learning for Verilog code generation (QiMeng-SALV) by leveraging code segments of functionally correct output signal to optimize RL training. Considering Verilog code specifies the structural interconnection of hardware gates and wires so that different output signals are independent, the key insight of QiMeng-SALV is to extract verified signal-aware implementations in partially incorrect modules, so as to enhance the extraction of meaningful functional rewards. Roughly, we verify the functional correctness of signals in generated module by comparing with that of reference module in the training data. Then abstract syntax tree (AST) is employed to identify signal-aware code segments which can provide meaningful functional rewards from erroneous modules. Finally, we introduce signal-aware DPO which is optimized on the correct signal-level code segments, thereby preventing noise and interference from incorrect signals. The proposed QiMeng-SALV underscores the paradigm shift from conventional module-level to fine-grained signal-level optimization in Verilog code generation, addressing the issue of insufficient functional rewards. Experiments demonstrate that our method achieves state-of-the-art performance on VerilogEval and RTLLM, with a 7B parameter model matching the performance of the DeepSeek v3 671B model and significantly outperforming the leading open-source model CodeV trained on the same dataset. Our code is available at https://github.com/zy1xxx/SALV.

Problem

• Addresses insufficient functional rewards in Verilog code generation
• Optimizes reinforcement learning using verified signal-level implementations
• Enhances functionally correct Verilog generation via signal-aware learning

Innovation

• Uses signal-level code segments for RL optimization
• Employs AST to extract verified signal implementations
• Introduces signal-aware DPO to prevent incorrect signal noise