Hardware-Accelerated Event-Graph Neural Networks for Low-Latency Time-Series Classification on SoC FPGA

2025-03-09

AI Summary

To address the real-time, low-latency, and low-power classification requirements for time-series signals from embedded edge sensors, this paper proposes an event-driven graph neural network (EGNN) hardware acceleration architecture tailored for SoC FPGAs. Methodologically, it innovatively integrates a cochlear implant model to construct a sparse event encoding mechanism, substantially reducing input redundancy; further, it introduces a dedicated EGNN hardware implementation paradigm supporting PS-PL co-scheduling and mixed fixed-/floating-point quantization. Experimental results on the SHD dataset show that the floating-point model achieves 92.7% accuracy with 10–67% fewer parameters than state-of-the-art (SOTA) approaches. The quantized model attains 92.3% accuracy—surpassing FPGA-based spiking neural network (SNN) baselines by 4.5–19.3%—while significantly reducing inference latency and logic resource consumption.

Technology Category

• Machine Learning: Hardware-aware ML
• Cognitive Modeling & Cognitive Systems: Neural Spike Coding
• Planning, Routing, and Scheduling: Optimization of Spatio-temporal Systems

Application Category

• Graph Algorithms and Modeling for the Web: Graph neural networks and deep learning approaches for Web-related graphs
• Systems and Infrastructure for Web, Mobile and WoT: Applied ML and AI for Web-based mobile applications
• User Modeling, Personalization and Recommendation: On-Device user modeling, personalization, and recommendation

Abstract

As the quantities of data recorded by embedded edge sensors grow, so too does the need for intelligent local processing. Such data often comes in the form of time-series signals, based on which real-time predictions can be made locally using an AI model. However, a hardware-software approach capable of making low-latency predictions with low power consumption is required. In this paper, we present a hardware implementation of an event-graph neural network for time-series classification. We leverage an artificial cochlea model to convert the input time-series signals into a sparse event-data format that allows the event-graph to drastically reduce the number of calculations relative to other AI methods. We implemented the design on a SoC FPGA and applied it to the real-time processing of the Spiking Heidelberg Digits (SHD) dataset to benchmark our approach against competitive solutions. Our method achieves a floating-point accuracy of 92.7% on the SHD dataset for the base model, which is only 2.4% and 2% less than the state-of-the-art models with over 10% and 67% fewer model parameters, respectively. It also outperforms FPGA-based spiking neural network implementations by 19.3% and 4.5%, achieving 92.3% accuracy for the quantised model while using fewer computational resources and reducing latency.

Problem

• Develop low-latency time-series classification on SoC FPGA.
• Convert time-series signals to sparse event-data for efficiency.
• Achieve high accuracy with fewer parameters and resources.

Innovation

• Hardware-accelerated event-graph neural networks
• Artificial cochlea model for sparse event-data conversion
• SoC FPGA implementation for low-latency, low-power processing