As a Principal Design Engineer – AI SoC / Subsystem Lead, you will be responsible for defining, implementing, and validating complex SoC IP blocks and subsystems, ensuring they meet stringent power, performance, and security requirements. You will collaborate across architecture, verification, and physical design teams to deliver high-quality silicon for next-generation AI solutions.

Architectural Leadership: Evaluate trade-offs across features, performance targets, power constraints, and system limitations.

Microarchitecture & RTL Development: Define and document microarchitecture for complex SoC IP blocks; implement RTL in Verilog/SystemVerilog, integrate at top level, and deliver synthesis- and timing-clean designs.

Verification Collaboration: Partner with verification teams to ensure comprehensive coverage and robust validation of all design aspects.

Timing & Physical Design Support: Develop and maintain timing constraints; guide physical design teams on synthesis, timing closure, and formal equivalence checks.

Silicon Bring-Up: Drive post-silicon validation, debug, and performance analysis.

Mentorship & Methodology: Mentor junior engineers and contribute to best practices for design methodology and quality.

Additional Responsibilities: Perform quality checks across RTL, timing, and power convergence. Apply secure development practices to address security threat models and objectives. Collaborate with IP providers for integration and validation at the SoC level. Drive compliance for smooth IP-to-SoC handoff.