In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will architect the control-plane software for the entire high-speed Physical Layer (PHY). You will lead the development of complex state machines for link training and auto-negotiation that allow Google’s AI clusters to communicate reliably at next-generation data rates.

Define the software architecture for multi-core embedded systems, manage memory maps, interrupt latency, and inter-processor communication (IPC).

Lead the implementation of industry-standard link training and auto-negotiation protocols for high-speed ethernet and custom interconnects.

Optimize firmware for time-to-link and power consumption, ensure the silicon stays within strict thermal envelopes during heavy AI training workloads.

Act as the primary firmware interface for the RTL design team to define register maps, APIs, and hardware or software boundaries.