About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Hardware Emulation Engineer, you will help develop and maintain emulation infrastructure, tools, and workflow methodologies supporting our ASIC projects.
Responsibilities
Create and support emulation models from Register-Transfer Level (RTL).
Drive system bring up on emulation platforms, debug test failures and simulation/emulation mismatches.
Bring up external Input/Output (I/O) interfaces (e.g., PCIe, Memories, SERDES, SPI, JTAG etc.) on the emulation platforms.
Develop and operate tests on the emulators and assist in bring-up processes from prototyping through post-silicon validation.
Contribute to ongoing methodology and automation improvements, constantly evolving and improving emulation efficiency and value.
Qualifications
Minimum
Bachelor's degree in Electrical Engineering or a related field or equivalent practical experience.
2 years of industry experience with RTL design (e.g., Verilog or System Verilog) and simulation (e.g., VCS, Incisive or Questa).
Experience with coding or scripting in C, C++, Perl, TCL or Python.
Experience with emulation systems (e.g., ZeBu, Palladium, Veloce), compilation, debugging, performance and methodology enhancements.
Preferred
Master's degree in Electrical Engineering or a related field.
Experience with RTL design (e.g., Verilog or System Verilog) and simulation (e.g., VCS, Incisive or Questa).
Experience with performance analysis/debug techniques.
Knowledge of external I/O interfaces like PCIe, DDR5, HBM, SPI, or JTAG etc.
Understanding of computer architecture including industry standard interfaces and memory subsystems.