In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a part of the Tensor Processing Unit (TPU) team, you will build machine learning accelerator ASICs for Google and positively impact Google’s products and billions of Google users across the globe.

Review chip specification and design, develop the integration plan with software and system partners, co-ordinate hardware and software delivery and demonstrate functionality.

Integrate and validate hardware and software designs, including first-party and third-party IPs, assist bringup of machine learning compute features, and develop firmware to help validate hardware functionality.

Utilize hardware/software co-simulation methodologies leveraging Register-Transfer Level (RTL) simulation, Emulation, FPGA environments as appropriate, architectural simulators or performance models as required to correlate performance.

Develop detailed test plans, based on design specifications coordinated with a cross-functional team (e.g., Design, Design Verification, Firmware, Compiler, Architecture).

Assist debug discussions with Design, Design Verification, Architecture teams and help root-cause functional failures and performance issues through the product development cycle, while improving validation coverage and sign-off processes for high-quality tapeout and production deployment.