About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
Responsibilities
Develop SystemVerilog RTL to implement logic for ASIC products.
Create and review design microarchitecture specifications.
Develop methodology and tooling for design automation.
Work with Design Validation (DV) teams to create test plans to verify, and debug design RTL.
Work with Physical Design teams to ensure design meets physical requirements and timing closure.
Qualifications
Minimum
PhD in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
Experience in any one domain of silicon engineering through internships, academic research, or publications (e.g., digital design basics, including synchronous and asynchronous logic, state machines, or bus protocols).
Experience in a scripting language such as Python or Perl.
Experience in Verilog or SystemVerilog.
Preferred
Experience with creating digital designs, including synchronous and asynchronous logic, state machines, and bus protocols.
Experience developing scripts or tooling for design automation.
Experience optimizing designs for performance, power or area.