About the job
The focus of this role is to work extensively on AMD AI/NPU processors, primarily on Power and Performance Validation and debug, along with AI software frameworks and application development to build end user cases.
Responsibilities
Power Performance validation for AI systems, primarily windows.
Power Performance Validation Test Plan creation, execution and automation
Power and performance automation for various Windows AI workloads at test app level, Real app level and for microkernels and benchmarks.
Collaborate closely with firmware, IP and SOC teams to validate NPU IP at IP level and system level for power and performance functionality across pre-silicon and post-silicon environments
Will be required to do FW prototyping, making changes in FW, compiling, test and debug for Power/perf prototyping.
Power kernel development and debug for AI accelerator/ NPU/GPU
AI applications development and debug, primarily on windows.
Debugging windows system using debug tools (wndbg), and traces for performance debugs will be frequently used.
Solid use of AI tools and agents for validation, debugging and optimization.
Demonstrates a strong understanding of power and performance concepts at the system level, including CPU, NPU, GPU, and memory.
Power performance debug and tuning experience for various workloads, understand workload sensitivities, and tune for most efficient performance.
Analyze issues spanning RTL, firmware, and software layers, driving root-cause analysis and working cross-functionally to resolution.
Contribute to the definition of firmware requirements and validation strategies to ensure robust coverage of real-world use cases.
Qualifications
Minimum
No minimum qualifications listed.
Preferred
Good understanding of SOC architecture, Firmware, OS and Application comprising the whole system.
Experience working with or validating low-level firmware (e.g., Power management FW, FreeRTOS, Zephyr, Microcontroller FW).
Strong understanding of hardware/firmware interfaces, including registers, interrupts, memory-mapped I/O, and sequencing.
Ability to read, debug, and reason about C/C++ firmware code in the context of hardware validation.
Experience collaborating with firmware or embedded software engineers to debug complex system-level issues.
Strong background in the C, C++ language, and Python,
Hands-on experience with graphics, SoC, or IP-level firmware used for bringing-up, configuration, or power/clock management.
Familiarity with post-silicon validation, firmware-assisted debug, or lab-based bring-up activities.
Experience validating systems where firmware plays a critical role in feature enablement and performance tuning.
Exposure to leadership or mentorship is an asset
Prior exposure to NPU / Windows based systems with exposure to CPU, GPU, NPU power, performance
Solid use of AI tools and agents for validation, debugging and optimization