About the job
This role develops, deploys, and owns the RTL-to-GDSII methodology the IP physical design team runs on, so a new block, node, or customer variant starts from a working flow instead of a cold start.
Responsibilities
- Develops, deploys, and owns the RTL-to-GDSII methodology for the IP physical design team
- Builds flows that production teams depend on daily
- Removes manual steps and makes PPA exploration repeatable
- Partners with design teams and EDA vendors
- Documents flows well enough that others can run them without you
Qualifications
Minimum
- 5+ years developing and supporting physical design methodology or CAD flows in production use
- Expertise with industry-standard tools (FusionCompiler/ICC2, Innovus/Genus, PrimeTime, RedHawk) and scripting languages (Tcl, Python, Perl)
- Deep understanding of advanced node methodology, low-power intent (UPF/CPF), clock tree synthesis, and signoff (EM/IR, DRC/LVS)
- Experience standing up flows for new technology nodes, PDKs, or foundry targets ahead of program need, and qualifying new EDA releases
Preferred
No preferred qualifications listed.