About the job
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is at the forefront of AI technology, building next-generation computers where memory is a key component. We're seeking an innovative Memory Architect to push the boundaries of our memory chiplet architecture for AI and CPU applications. You'll work closely with fellow architects, cross-functional teams, and external partners to explore advanced memory technologies.
Responsibilities
Define the architecture and micro-architecture specifications for memory and I/O chiplets, focusing on state-of-the-art memory technology for AI and CPU applications.
Explore and evaluate next-generation memory technologies, analyzing trade-offs across key metrics like bandwidth, latency, and power to develop a strategic roadmap.
Develop and own a detailed performance and power modeling infrastructure to enable data-driven decisions for high-throughput, low-latency memory architectures.
Work closely with SoC design/verification, physical design, packaging, and systems engineering teams to ensure seamless integration. You will also communicate frequently with external partners and customers.
Qualifications
Minimum
You have a deep understanding of JEDEC standard DRAMs (GDDR, HBM, LPDDR, DDR) and their specifications.
You bring 10+ years of experience in memory system architecture, scheduling algorithms, and controller architecture exploration and design.
You have hands-on experience building performance/power simulators or developing memory IPs in HDL.
Preferred
Experience with 3D-stacking, advanced packaging, custom memory, DFI, die-to-die interfaces, storage, and I/O protocols is a huge plus.
A deep understanding of memory reliability and security is a strong plus.
A PhD with a focus on computer architecture or a strong research background (or a publication track record) is a strong plus.