About the job
The Machine Learning Hardware Accelerator team is seeking an experienced and talented Hardware Design & Architecture Lead. This role will drive the definition and analysis of next-generation ML hardware accelerator architectures, with a special emphasis on vision applications for mobile and emerging products.
Responsibilities
Architect high-performance, power-efficient ML hardware accelerator designs, especially for computer vision workloads (e.g., image classification, object detection, video analytics).Analyze and optimize hardware for performance, power, and area (PPA) tradeoffs.Define hardware micro-architecture for efficient implementation of ML algorithms.Lead HW IP development, working closely with RTL design, verification, synthesis and physical design teams to improve PPA.Collaborate closely with global hardware, software, and systems teams to deliver best-in-class ML solutions.Work with cross-functional teams (HW design, verification, SW, systems, marketing, product planning) to align architecture with product goals.Use models, simulators, profilers, and real hardware to justify architectural decisions quantitatively.Apply knowledge of CPUs, GPUs, DSPs, memory, and bandwidth analysis to ML hardware design.Communicate results and technical issues effectively with leads and peers.Invent and file patents for innovative hardware solutions.
Qualifications
Minimum
Experience in hardware development for ML, multimedia, or accelerator technologies (vision, imaging, video, display, audio, etc.).Experience in system or chipset development for SoC products, preferably in the mobile market.Familiarity with OS principles and HW/SW interaction.Experience with SoC bus, interconnect, and memory technologies.MS Degree required with 15+ years industry experience in one or more of the following areas:Architecture/micro-architecture of ML or multimedia cores.Experience with ML frameworks and accelerator standards (e.g., TensorFlow Lite, ONNX).VLSI design and verification (Verilog/SystemVerilog/HLS).C/C++/SystemC programming.Hands-on experience with simulators and performance/power models.Scripting & automation skills.
Preferred
Deep domain knowledge in ML for vision (image/video processing, neural network architectures for vision).Experience collaborating with global teams across multiple time zones and cultures.Experience working with synthesis and physical design teams for HW IP development and PPA improvement.Excellent communication, documentation, and presentation skills.Demonstrated technical and people leadership.