About the job
We’re looking for a RTL Engineer to design and implement key compute, memory, and interconnect components for our custom AI accelerator. You’ll work closely with architecture, verification, physical design, and ML engineers to translate AI workloads into efficient hardware structures. This is a hands-on design role with significant ownership across definition, modeling, and implementation.
Responsibilities
Produce clean, production-quality microarchitecture and RTL for major accelerator subsystems
Contribute to architectural studies including performance modeling and feasibility analysis.
Collaborate with software, simulator, and compiler teams to ensure hardware/software co-design and workload fit.
Partner with DV and PD to ensure functional correctness, timing closure, area/power targets, and clean integration.
Build and review performance and functional models to validate design intent.
Participate in design reviews, documentation, and bring-up support across the full silicon lifecycle.
Qualifications
Minimum
Graduate-level research or industry experience in computer architecture, AI/ML hardware–software co-design, including workload analysis, dataflow mapping, or accelerator algorithm optimization.
Expertise writing production-quality RTL in Verilog/SystemVerilog, with a track record of delivering complex blocks to tape-out.
Experience developing hardware design models or architectural simulators, ideally for AI/ML or high-performance compute systems.
Familiarity with industry-standard design tools (lint, CDC/RDC, synthesis, STA) and methodologies.
Ability to work cross-functionally with architecture, ML systems, compilers, and verification teams.
Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits.
Preferred
Strong problem-solving skills and ability to think across abstraction layers, from algorithms to circuits.
Passion for building industry-leading massive-scale hardware systems.