About the job
We are looking for a Sr. Design Engineer – IP Office to work in the dynamic Microsoft Artificial Intelligence Silicon Engineering team. Be a highly motivated self-starter with deep semiconductor IP development expertise who is excited to grow from technical leadership into program leadership. The role is responsible for driving cross-functional execution, managing risks and dependencies, ensuring high-quality IP delivery, and enabling successful product outcomes at scale.
Responsibilities
Drive IP selection, qualification, and adoption for AI SoC programs, ensuring alignment with product requirements and SoC landing zones.
Lead IP acquisition (through IP license/SOW), release management, quality assurance, and integration of third-party and internal IPs.
Establish and scale robust processes for IP release, updates, QA, integration, and pre/post-silicon validation.
Track third-party and internal IP releases and updates, ensuring timely release of collaterals to internal SOC teams for integration and issue resolution.
Partner with Architecture, Design, Physical Design (PD), Design for Test (DFT), Validation, Packaging and Board Design teams to optimize design tradeoffs and drive integration quality reviews.
Drive cross-functional resolution of pre- and post-silicon IP issues and integration challenges.
Provide technical leadership through collaboration, influence, and effective stakeholder engagement across engineering organizations and vendors.
Qualifications
Minimum
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience
Preferred
4+ years of experience in Integration and debug of IPs in major CPU, GPU or AI accelerator SoC’s and close interactions with Major IP vendors and suppliers of SoCs
4+ years Design experience either in IP development or in SoC level Integration of at least one of the following areas: SRAM design, Register Files and Memory Compilers; High Speed serial and/or Parallel IOs; Sub-system and SoC integration; Detail understanding of IP collaterals required for front end, physical design and DFT integration into SOC
Track record of successful tape outs in deep sub-micron technologies
2+ years of experience in IP office functions of a major CPU, GPU or AI SoC
Established reputation in interactions with leading suppliers of IPs in 112G/224G class Ethernet, PCIe 5/6, HBM3/4, temperature, voltage and process monitors
Scripting language such as Python or Perl
Knowledge of Front-end and back-end IP Integration flows in a SoC
Experience working with customers, external IP vendors and silicon foundry
Communication skills, self-motivation, and ability to collaborate with architecture, Front-end, Physical design and post-silicon teams in Microsoft