About the job
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. We are looking for a Principal Physical Design Engineer to join the team to work on Microsoft Next-Gen AI SOC chip. If hired, you will be responsible for delivering TFM (tool, flow and methodology) of Physical Design tasks at block, sub-chip, and/or full-chip level.
Responsibilities
Lead the PnR convergence recipe development for designs at blocks/subsystem and subchip level
Develop and implement methodologies and strategies to improve physical design efficiency and performance
Develop and implement methodologies and strategies to sign off blocks, subsystem/Subchip in the areas of static timing analysis, physical verification, functional logics equivalence, low power verification and electromigration and IR drop
Implementation of functional and timing ECO with least physical design impact
Design and implement the global clocking scheme at SOC and sub chip levels
Stay current with industry trends and emerging technologies to continuously improve physical design processes and methodologies
Installation and quality check of internal and external IP collaterals for use by Physical Design execution team
Conduct physical design reviews, identify and resolve design issues, and provide guidance to junior engineers.
Qualifications
Minimum
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience.
Ability to meet Microsoft, customer and/or government security screening requirements are required for this role.
Preferred
Bachelor's or Master’s in Electrical or Computer Engineering or related field with 10+ years of experience
Experience in tapeouts of complex ASICs in leading edge technology
10+ years of experience in blocks level place and route and
Expertise in one or more of physical design EDA tools such as Synopsys Fusion Compiler, PrimeClosure, Primetime, Formality, VCLP, Star-RC, Redhawk SC, and Cadence Innovus; Siemens Calibre.
Strong understanding of semiconductor design principles, methodologies, and tools.
Proven track record of successfully leading physical design projects and delivering high-quality semiconductor products
Adequate scripting skillsets in TCL and Python
Good understanding of foundry tech files and rule decks