About the job
As a Research Scientist, you'll setup large-scale tests and deploy promising ideas quickly and broadly, managing deadlines and deliverables while applying the latest theories to develop new and improved products, processes, or technologies. The overall job responsibility is modeling of quantum gates based on superconducting qubits, with the focus on two-qubit gates with tunable couplers, using either parametric or non-parametric coupling. This includes developing investigative and numerical models of various physical processes leading to gate errors. Numerical simulations using these models are then compared with experimental results and used for gate optimization. The work will be in close collaboration with the hardware team and will include analysis and theoretical understanding of experimental data. In this role, you will be focused on advancing the capabilities of quantum computing and enabling meaningful applications.
Responsibilities
Simulate two-qubit gates for transmons, and model tunable couplers.
Develop physics-based models for gate error mechanisms, including gate errors due to pulse distortions.
Optimize system parameters numerically.
Analyze experimental data on two-qubit gates.
Propose and analyze new gates with advanced performance.
Qualifications
Minimum
PhD degree in Physics or Electrical Engineering, or equivalent practical experience.
Experience with coding in Python.
One or more scientific publication submissions for conferences, journals, or public repositories related to quantum computing.
Preferred
Experience with superconducting qubits, including modeling of two-qubit gates, and gates calibration and characterization.
Experience in collaboration with experimentalists on quantum projects or analyzing/modeling experimental data.
Experience with tunable couplers, parametric gates and flux/charge noise analysis.
Experience in quantum error correction with superconducting qubits.
Experience in modeling microwave pulse distortions and its impact on gate error.
Experience in modeling multi-chip interconnection and gate operation.