About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Design Engineer, Custom Circuits and Static Random-Access Memorys (SRAMs) you will collaborate with circuit design, SRAM, physical design, technology, and architecture leads to deliver ASIC’s and SoC’s.
Responsibilities
Evaluate, analyze, implement, and integrate SRAMs, other memories (such as multiport register files), and custom circuits.
Drive proper IP integration and margins with the physical design team.
Work with our foundry and IP partners plus our technology, physical design, and architecture teams in advanced CMOS nodes to optimize our products for Power Performance Area (PPA), schedule, and reliability.
Drive and support test chip design, execution, and validation of critical circuit IPs.
Design and build custom circuits at the transistor and gate levels to support physical design and power-performance-area optimization.
Drive development of a leading edge technology platform for custom, high performance ASIC’s and SoC’s, from design through manufacturing, packaging, and test.
Qualifications
Minimum
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
5 years of experience in Circuit Design, Physical Design (RTL-to-GDS), or Technology Development, including advanced nodes (e.g., 7nm or below).
Experience with custom circuit/IP and physical design, including Place and Route (PNR) and Static Timing Analysis (STA).
Experience with SPICE and transistor level design in advanced nodes.
Experience in CMOS device physics, finfet/GAA/nanosheet architectures, and layout parasitics.
Experience in scripting and automation using Tcl and Python (or Perl).
Preferred
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
10 years of experience delivering optimized custom circuits, memories, IPs, and PNR blocks for product tapeout.
Experience working with major foundry technology files (PDKs), standard cell libraries, metal stacks, and other features.
Understanding of characterization and verification of standard cells/SRAMs/register files, including knowledge of power, noise, variation, and IR analysis.
Understanding of collaterals for frontend and backend design teams.
Strong documentation and presentation skills to communicate efficiently with teammates and vendors/partners.