In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. Be part of the TPU team that builds Machine Learning Accelerator ASICs for Google and positively impact Google’s products and billions of Google users across the globe.

Review chip specifications and designs, developing integration plans with software and system partners while coordinating hardware/software delivery.

Lead the bringup of ML compute features, integrating and validating complex hardware/software designs, including third-party IPs.

Develop validation firmware to verify hardware functionality.

Execute hardware-software co-simulation methodologies leveraging RTL, emulation, and field-programmable gate array (FPGA) environments.

Utilize architectural simulators and performance models to correlate results.

Design validation tests and microbenchmarks to verify IP functionality and performance.

Author comprehensive test plans in coordination with cross-functional teams including Design, Design Verification (DV), Firmware, and Architecture.

Own debug discussions with Design/DV/Software/Architecture teams and help root cause functional failures and performance issues throughout the product development cycle.

Improve validation coverage and sign-off processes for high-quality tapeout and production deployment.