About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will have the opportunity to contribute to transformative projects at the forefront of quantum computing research. You will contribute to the quantum team’s mission by developing digital electronics for the control and readout of our quantum computers. You will be part of a team developing electronics for our current and next generation quantum computers and, in this context, will own development projects, working with quantum engineers, software engineers, and other hardware engineers to scope out, architect, and implement FPGA based systems. You will have a deep understanding of the FPGA development cycle, from microarchitecture, RTL development, verification, bit file generation to hardware debugging. You will take ownership of projects and deliver reliable systems. Adept debugging skills on FPGAs and debugging failures after deployment is essential for this role. You will be passionate to guide a lean team to achieve team’s goals and employ effective communication skills to facilitate seamless collaboration across multidisciplinary teams.
Responsibilities
Profile and optimize FPGA designs to improve performance, latency, and power efficiency while maintaining design documentation and communicate progress and findings effectively in meetings and reviews.
Identify and resolve issues in RTL and post-synthesis stages using debugging tools and methodologies.
Create testbenches and plans to verify FPGA designs, ensuring functionality and correctness through simulations and testing.
Collaborate with quantum physicists and hardware engineers to define and implement Scalable FPGA architectures optimized for quantum computing systems.
Develop efficient microarchitecture, RTL code using Verilog/Systemverilog to realize complex digital logic designs on FPGAs.
Utilize tools like Vivado or Quartus Prime to synthesize.
Qualifications
Minimum
Bachelor’s degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience.
4 years of experience in Field Programmable Gate Array (FPGA) design and development.
4 years of experience with RTL design using Verilog or systemVerilog.
Preferred
Master's or PhD degree in Electrical Engineering, Computer Engineering, Physics, or a related field.
1 year of experience in technical leadership.