In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be working on ASIC development, validation, software, tools, and methodologies and will have the ability to push the boundaries of chip-development and hardware/software integration and validation.

Lead hardware, software, and system integration for custom silicon, bridging architecture, design, and compiler teams to ensure platform delivery.

Own functional and performance validation requirements, ensuring successful demonstration across tape-out and post-silicon phases.

Drive ML compute feature bring-up by integrating first and third-party IPs and developing hardware-validating firmware.

Execute HW-SW co-simulation strategies utilizing RTL simulation, emulation, and FPGA environments to streamline silicon validation.

Design microbenchmarks and detailed validation plans based on cross-functional design specifications to verify IP functionality and performance.