About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be responsible for turning communication theory into efficient, bit-exact silicon logic. You will take high-level models and transform them into the high-speed Digital Signal Processing (DSP) blocks that sit at the heart of our next-gen architecture.
Responsibilities
Design and implement DSP algorithms for high-speed PHYs, focusing on FFE/DFE and timing recovery loops.
Perform rigorous fixed-point analysis to minimize bit-width (Area/Power) while maintaining the required Signal-to-Noise Ratio (SNR).
Develop bit-exact C++/SystemC models to verify RTL against architectural intent.
Qualifications
Minimum
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
10 years of industry experience in Digital Signal Processing (DSP) design or High-Speed Digital Logic design.
Experience implementing digital blocks for Communication Systems or PHY (Physical Layer) e.g., filters, interpolators, or timing recovery.
Experience in MATLAB, Python, or C++.
Preferred
Master's or PhD degree in Electrical Engineering, Computer Engineering, or a related technical field.
Experience with FinFET process nodes (5nm, 3nm) and Timing Closure at GHz frequencies.
Experience with UVM verification environments.