About the job
In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will join a team working on SoC-level RTL design for our TPU accelerators. In this role, you will work on top-level RTL, architecture, design and implementation of global communication busses, and integration of ASIC designs. You will grow in a highly cross-functional and central role that will require leadership to drive interactions with numerous ASIC development teams. You will own deliverables to the cross-functional teams (i.e. Physical Design, Verification, Validation, Firmware) at various project milestones. You will also be directly involved in defining and creating methodologies that enable a highly efficient design environment for all ASIC engineers. You will work within the team to manage SoC IP integration, participate in SoC level sign-off activities, and participate in layout design decisions. In this role, you will utilize and design script-based tools and flows to speed SoC construction and signoff and previous experience architecting RTL solutions employing software based construction, instantiation, customization and generation of RTL is highly desirable.
Responsibilities
Develop strategies for system segmentation to enable programmatic assembly of custom solutions based off user design intent.
Architect RTL systems to allow for automated optimization of RTL performance, power and area based off solution requirements.
Build and implement RTL code for various digital blocks, including control logic, and on-chip data paths.
Engage in SoC IP integration and sign-off activities.
Contribute to the development and improvement of design flows, tools and methodologies.
Qualifications
Minimum
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
2 years of experience architecting RTL solutions employing software based construction, instantiation, customization or generation of RTL.
Experience with SOC implementation standards and interfaces (i.e. AXI).
Experience with scripting languages (i.e. Tcl, Python or Perl).
Experience with digital design, including synchronous and asynchronous logic, state machines, and bus protocols.
Preferred
Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
5 years of experience with SOC implementation standards and interfaces (i.e. AXI).
Experience with UPF, CDC, RDC, RTL Linting and LEC is desirable.
Proficiency in Python or Perl for automating design scripts and analyzing complex clock-tree data.
Ability to lead cross-functional efforts from initial specification through silicon bring-up.